Subarray control and subarray cell access in a memory module

Details Subarray control and subarray cell access in a memory module Subarray control and subarray cell access in a memory module

2005-02-01

2005-02-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S205000

Reexamination Certificate

active

06850456

ABSTRACT:
The present invention provides a subarray control apparatus and method. The subarray control includes a wordline driver configured to generate a wordline activation signal, and a write/read control signal generator configured to generate a write/read enable signal. In addition, the subarray control includes a timing generator configured to generate a wordline timing signal input to the wordline driver and a write/read timing signal input to the write/read control signal generator. The wordline activation signal is based on enable data captured by a first transparent latching circuit and the wordline timing signal generated within the subarray. The write/read enable signal is based on enable data captured by a second transparent latching circuit and the write/read timing signal generated within the subarray. Accessing subarray cells in a memory module and a memory module incorporating the subarray control are also disclosed.

REFERENCES:
patent: 5406526 (1995-04-01), Sugibayashi et al.
patent: 5615168 (1997-03-01), Lattimore et al.
patent: 6115310 (2000-09-01), Netis et al.
patent: 6512718 (2003-01-01), Lee

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