Electronic device and method of manufacturing the same, and...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S773000, C257S776000

Reexamination Certificate

active

06853080

ABSTRACT:
A plurality of lands are arranged in rows. The lands in adjacent rows are disposed in a staggered arrangement. A first interconnecting line is pulled out from each of the lands. Each of the lands is wider than the first interconnecting line in the row direction. A plurality of electrical connection sections are arranged in rows. The electrical connection sections in adjacent rows are disposed in a staggered arrangement. The lands are electrically connected with the electrical connection sections so as to overlap. Each of the electrical connection sections is a part of a second interconnecting line, and an insulating layer is formed between the second interconnecting lineing pattern other than the electrical connection sections and the first interconnecting lineing pattern.

REFERENCES:
patent: 6775153 (2004-08-01), Hashimoto
patent: 05-265022 (1993-10-01), None
patent: 08-139126 (1996-05-01), None
patent: 10-253980 (1998-09-01), None

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