Frequency comparator with hysteresis between locked and...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator

Reexamination Certificate

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C331S00100A, C331S018000, C331SDIG002, C327S043000, C375S376000

Reexamination Certificate

active

06859107

ABSTRACT:
A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

REFERENCES:
patent: 4594564 (1986-06-01), Yarborough, Jr.
patent: 4773085 (1988-09-01), Cordell
patent: 4970581 (1990-11-01), O'Gwynn
patent: 5996030 (1999-11-01), Ofer
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6442225 (2002-08-01), Huang
patent: 6667643 (2003-12-01), Ko
patent: 6683930 (2004-01-01), Dalmia
patent: 6700944 (2004-03-01), Chlipala et al.
Lee, C. Yoo, W. Kim, S. Chai, and W. Song, “A 622Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phas Detector Array,” inIEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 198-199.
Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, “A 1.0625 Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,” inIEEE ISSC Dig. Tech. Papers, Feb. 1997, pp. 238-239.
R. Gu, J. M. Tran, H.-C. Lin, A.-L. Yee, and M. Izzard, “A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver,” inIEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 352-353.
T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, and T. Ishikawa, “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,”IEEE J. Solid-State Circuits, vol. 29 (Dec. 1994), pp. 1491-1496.
Efendovich, Y. Afek, C. Sella, and Z Bikowsky, “Multifrequency Zero-Jitter Delay-Locked Loop,”IEEE J. Solid-State Circuits, vol. 29, No. 1 (Jan. 1994), pp. 26-70.
S. Sidiropoulos, and M. A. Horowitz, “A Semi-Digital Dual Delay-Locked Loop,”IEEE J. Solid-State Circuits, vol. 32, No. 11, (Nov. 1997), pp. 1683-1692.
Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M.-K Kim, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,”IEEE J. Solid-State circuits, vol. 35, (Mar. 2000), pp. 377-384.
Ian A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock generator with 5 to 100 MHz of Lock Range for Microprocessors”,IEEE Journal of Solid-State Circuits, vol. SC-27, (Nov. 1992), pp. 1599-1607.

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