System and method for source defined packet routing

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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C370S400000

Reexamination Certificate

active

06934283

ABSTRACT:
A data communication system and method are provided to communicate in a multiprocessor interconnection network or other network. In one embodiment, the present system includes a number of logical circuits that are located in a number of nodes interconnected in a multiprocessor interconnection network. In this regard, the nodes include at least one source node, at least one destination node, and at least one intermediate node. The logical circuits include source logic located in the source nodes to identify data routes between respective source nodes and destination nodes through the one or more intermediate nodes. The data routes are specified by at least one destination port value and a current hop count that are attached to a data packet to be transmitted between respective source and destination nodes. The logical circuits also include routing logic in the intermediate nodes to route the data packets along the data routes, and destination logic in the destination node to detect a final destination of the data packet. The various embodiments of the present invention also include return routing logic in the intermediate nodes to record a return route in the data packet.

REFERENCES:
patent: 5577204 (1996-11-01), Brewer et al.
patent: 5721819 (1998-02-01), Galles et al.
patent: 6160811 (2000-12-01), Partridge et al.
patent: 6230252 (2001-05-01), Passint et al.
Hu et al. A Queueing Model for Wormhole routing with Timeout. IEEE. Jul. 1995. pp. 584-593.
Stallings, William. “Data and Computer Communications”. Prentice-Hall. Copyright 1997. pp. 541-546.
Mike Galles, “Scalable Pipelined Interconnect for Distributed Endpoint Routing: The SGI SPIDER chip,” Proceedings of Hot Interconnect 1996, pp. 141-146.

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