Sub-lithographics opening for back contact or back gate

Details Sub-lithographics opening for back contact or back gate Sub-lithographics opening for back contact or back gate

2005-12-06

2005-12-06

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S347000, C257S352000, C438S517000

Reexamination Certificate

active

06972448

ABSTRACT:
A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

REFERENCES:
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6043535 (2000-03-01), Houston
patent: 6064589 (2000-05-01), Walker
patent: 6342717 (2002-01-01), Komatsu
patent: 6383904 (2002-05-01), Yu
patent: 6391695 (2002-05-01), Yu
patent: 6580132 (2003-06-01), Chan et al.
patent: 6759315 (2004-07-01), Furukawa et al.

Affiliated with

Also associated with

Rating

Sub-lithographics opening for back contact or back gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sub-lithographics opening for back contact or back gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sub-lithographics opening for back contact or back gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3473972