Split-gate flash EEPROM cell and array with low voltage erasure

Details Split-gate flash EEPROM cell and array with low voltage erasure Split-gate flash EEPROM cell and array with low voltage erasure

1993-04-16

1994-08-30

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 365900, 257317, 257314, 257320, 257321, H01L 2968, G11C 1134

Patent

active

053434242

ABSTRACT:
Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.

REFERENCES:
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 4958321 (1990-09-01), Chang
patent: 5057886 (1991-10-01), Riemenschneider et al.
patent: 5168465 (1992-12-01), Harari
patent: 5194925 (1993-03-01), Ajika et al.
"A Flash-Erase EEPROM Cell With An Asymmetric Source and Drain Structure", by H. Kume et al., IEDM, 25.8, 1987, pp. 560-563.
"A 128K Flash EEPROM Using Double-Polysilicon Technology", by G. Samacisa et al., IEEE J. Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, 676-683.

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