Non-volatile memory architecture and method thereof

Details Non-volatile memory architecture and method thereof Non-volatile memory architecture and method thereof

Filed on

2005-02-08

Date issued

2005-02-08

Examiner

Phung, Anh (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular biasing

Other Related Categories

C365S185180

Type

Reexamination Certificate

Status

active

Patent number

06853586

Description

ABSTRACT:
A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge. Using the bit line in this manner limits the electric field to which the oxide of the bit cell is exposed, thereby lessening the amount of read disturb, while also improving the magnitude of the read mode signal and, therefore, improving overall tolerance of the read disturb effect.

REFERENCES:
patent: 5789776 (1998-08-01), Lancaster et al.
patent: 6031760 (2000-02-01), Sakui et al.
patent: 6122196 (2000-09-01), Tanaka et al.
patent: 6480418 (2002-11-01), Tanaka et al.
patent: 6512703 (2003-01-01), Sakui et al.
patent: WO 9530244 (1995-11-01), None
“Why SONOS?”, Loren Lancaster, Cypress Semiconductor 2001.

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