Method and apparatus for restoring registers after...

Details Method and apparatus for restoring registers after... Method and apparatus for restoring registers after...

2005-05-03

2005-05-03

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S219000

Reexamination Certificate

active

06889316

ABSTRACT:
In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.

REFERENCES:
patent: 5644742 (1997-07-01), Shen et al.
patent: 5706459 (1998-01-01), Atsushi
patent: 6263416 (2001-07-01), Cherabuddi
patent: 6425072 (2002-07-01), Meier et al.
patent: 6442678 (2002-08-01), Arora

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