Low-jitter delay cell

Details Low-jitter delay cell Low-jitter delay cell

2005-05-17

2005-05-17

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S287000

Reexamination Certificate

active

06894552

ABSTRACT:
A differential delay cell is disclosed. The delay cell includes a voltage bus and a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output. A current source is disposed at the current node while a differential diode-connected load is disposed between the differential pair and the voltage bus. The differential diode-connected load comprises at least one n-channel MOS transistor configured as a diode.

REFERENCES:
patent: 4659979 (1987-04-01), Burnham et al.
patent: 4800303 (1989-01-01), Graham et al.
patent: 5714912 (1998-02-01), Fiedler et al.
patent: 5789981 (1998-08-01), Singer et al.
patent: 5994939 (1999-11-01), Johnson et al.
patent: 6081166 (2000-06-01), Katakura
patent: 6157266 (2000-12-01), Tsai et al.
patent: 6175260 (2001-01-01), Cho
patent: 6348839 (2002-02-01), Aramaki
patent: 6686788 (2004-02-01), Kim et al.

Affiliated with

Also associated with

Rating

Low-jitter delay cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-jitter delay cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-jitter delay cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3438149