Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2005-03-08
2005-03-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S455000
Reexamination Certificate
active
06864155
ABSTRACT:
A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods, are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.
REFERENCES:
patent: 5021843 (1991-06-01), Ohmi
patent: 5374329 (1994-12-01), Miyawaki
patent: 5405802 (1995-04-01), Yamagata et al.
patent: 5453394 (1995-09-01), Yonehara et al.
patent: 5670411 (1997-09-01), Yonehara et al.
patent: 5767020 (1998-06-01), Sakaguchi et al.
patent: 5773355 (1998-06-01), Inoue et al.
patent: 5841171 (1998-11-01), Iwamatsu et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5882532 (1999-03-01), Field et al.
patent: 5910672 (1999-06-01), Iwamatsu et al.
patent: 6010921 (2000-01-01), Soutome
patent: 6037634 (2000-03-01), Akiyama
patent: 6215155 (2001-04-01), Wollesen
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 6265327 (2001-07-01), Kobayashi et al.
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6313014 (2001-11-01), Sakaguchi et al.
patent: 6340829 (2002-01-01), Hirano et al.
patent: 6350703 (2002-02-01), Sakaguchi et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6433401 (2002-08-01), Clark et al.
patent: 6509613 (2003-01-01), En et al.
patent: 6512244 (2003-01-01), Ju et al.
patent: 6531375 (2003-03-01), Giewont et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6541861 (2003-04-01), Higashi et al.
patent: 6552396 (2003-04-01), Bryant et al.
patent: 6552496 (2003-04-01), Yamazaki
patent: 6610615 (2003-08-01), McFadden et al.
patent: 6642579 (2003-11-01), Fung
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6680243 (2004-01-01), Kamath et al.
patent: 20010020722 (2001-09-01), Yang
patent: 20020011670 (2002-01-01), Higaski et al.
patent: 20020070454 (2002-06-01), Yasukawa
patent: 20020134503 (2002-09-01), Hussinger et al.
patent: 20030085424 (2003-05-01), Bryant et al.
Bernstein et al.,,Ch. 3: SOI Device Electrical Properties, § 3.4 Floating Body Effects, SOI Circuit Design Concepts, pp. 34-53 (Kluwer Academic Publishers, pre-Aug. 2001).
Kennedy Jennifer M.
Micro)n Technology, Inc.
Wells St. John P.S.
LandOfFree
Methods of forming silicon-on-insulator comprising... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming silicon-on-insulator comprising..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming silicon-on-insulator comprising... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3436007