Integrated circuit isolation structure for suppressing high-freq

Details Integrated circuit isolation structure for suppressing high-freq Integrated circuit isolation structure for suppressing high-freq

1996-04-04

1997-04-22

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257500, 257544, 257549, 257550, 257547, 257929, H01L 2704

Patent

active

056231598

ABSTRACT:
An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

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patent: 5336915 (1994-08-01), Fujita et al.
patent: 5394007 (1995-02-01), Reuss et al.

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