Flash memory for improving write access time

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185050, C365S230080, C365S189070, C365S239000

Reexamination Certificate

active

06917543

ABSTRACT:
A flash memory including a flash memory cell array, a page buffer, a comparator circuit, and a verify flag buffer. The flash memory cell array includes a plurality of blocks. The page buffer temporarily stores therein write data received from an external system. The page buffer includes pages. The comparator circuit executes pre-verification through comparing data stored in the page buffer with data stored in addressed one of the blocks. The verify flag buffer stores therein verify flags respectively associated with the pages. Each of the verify flags is switched in response to update of associated one of the pages. The comparator circuit executes pre-verification with respect to one of the pages, the one being associated with unswitched one of the verify flags, while skipping pre-verification with respect to another of the pages associated with the switched one of the verify flags.

REFERENCES:
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patent: 6751118 (2004-06-01), Tran et al.
patent: 61-122770 (1986-06-01), None
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patent: 2000-276883 (2000-10-01), None
patent: 2000-285092 (2000-10-01), None
patent: 2000-285686 (2000-10-01), None

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