Robust interlocking via

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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Details

C257S774000, C257S775000, C257S780000, C257S781000, C257S698000

Reexamination Certificate

active

06946737

ABSTRACT:
The invention provides a via with improved resistance to failures due to delamination voids. In one embodiment, the via may extend from above to below a bottom conductor and include an anchor section. The anchor section may mechanically interlock the via with the bottom conductor to prevent the via from being detached from the bottom conductor.

REFERENCES:
patent: 5129142 (1992-07-01), Bindra et al.
patent: 5191709 (1993-03-01), Kawakami et al.
patent: 5293504 (1994-03-01), Knickerbocker et al.
patent: 6079100 (2000-06-01), Farquhar et al.
patent: 6335565 (2002-01-01), Miyamoto et al.
patent: 6441494 (2002-08-01), Huang et al.

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