Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2005-04-19
2005-04-19
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S047000, C327S115000, C327S117000
Reexamination Certificate
active
06882698
ABSTRACT:
In one embodiment, as an example, N/M (=3.33333 . . . ) dividing is performed assuming M=3, N=10. That is, the frequency of the input signal CK is converted to the frequency of 1/3.33333 . . . times. Here, it is assumed that the frequency dividing number is 3.33333 . . . In this case, 3(=n) dividing is combined with 4(=n+1) dividing to perform the dividing, and accordingly a signal of a desired frequency can be obtained. In response to the output DOUT of the frequency divider, an n dividing counter counts the number of performed n-dividing operations and an n+1 dividing counter counts the number of performed n+1-dividing operations. An adder outputs the frequency dividing number (n) or (n+1). A frequency divider uses the frequency dividing numbers to divide an arbitrary frequency signal CK.
REFERENCES:
patent: 5224132 (1993-06-01), Goldberg
patent: 2001-251181 (2001-09-01), None
Takanobu Mukaide; Audio Clock Restoring Apparatus and Audio Clock Restoring Method; U.S. Appln. No. 10/195,437, filed Jul. 16, 2002 P. N. 6670857.
Finnegan Henderson Farabow Garret & Dunner, L.L.P.
Kabushiki Kaisha Toshiba
Wambach Margaret R.
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