State delayed technique and system to remove tones of...

Details State delayed technique and system to remove tones of... State delayed technique and system to remove tones of...

2005-03-08

2005-03-08

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

06864819

ABSTRACT:
A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z−1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

REFERENCES:
patent: 6124813 (2000-09-01), Robertson et al.
patent: 6292124 (2001-09-01), Hanada et al.
patent: 6466153 (2002-10-01), Yu
patent: 6518899 (2003-02-01), Yu
patent: 6545623 (2003-04-01), Yu
patent: 6577261 (2003-06-01), Brooks et al.
patent: 6583742 (2003-06-01), Hossack
patent: 6720897 (2004-04-01), Wang
patent: 20020180629 (2002-12-01), Liu et al.
patent: 1 202 459 (2002-05-01), None
patent: 2 356 301 (2001-05-01), None
patent: WO 2004006440 (2004-01-01), None
Kwan, Shuffler Apparatus and Related Dynamic Element Matching Technique for Linearization of Unit-Element Digital to Analog Converters, Fig. 2a, US 2003/0137439, 2003.
Yasuda et al., “A Third-Order Δ-Σ Modulator Using Second-Order Noise-Shaping Dynamic Element Matching,” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, pp. 1879-1886, IEEE (Dec. 1998).
Kwan et al., “A Stereo Multibit ΣΔ DAC with Asynchronous Master-Clock Interface,” IEEE Journal of Solid-State Circuits, vol. 31, No. 12, pp. 1881-1887, IEEE (Dec. 1996).
Adams et al., “A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling,” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, pp. 1871-1878, IEEE (Dec. 1998).
Welz et al., “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters.” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, No. 11, pp. 1014-1027, IEEE, (Nov. 2001).
Grilo et al., “A 12-mW ADC Delta-Sigma Modulator With 80 dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver,” IEEE Journal of Solid-State Circuits, vol. 37, No. 3, pp. 271-278, IEEE (Mar. 2002).
Ian Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing vol. 44, No. 10 pp. 808-817, IEEE (Oct. 1997).
Norsworthy et al., Delta-Sigma Data Converters: Theory, Design and Simulation, pp. 185-186, IEEE Press, 1999.
Zelniker et al., Advanced Digital Signal Processing: Theory and Applications, pp. 357-364, Marcel Dekker, Inc. (1994).
Morteza Vadipour, “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Σ-Δ Modulators,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, No. 11, pp. 1137-1144, IEEE (Nov. 2000).
Chen et al., “Some Observations on Tone Behavior in Data Weighted Averaging,” Proceedings of the 1998 International Symposium on Circuits and Systems, vol. 1, pp. 500-503, IEEE (1998).
Chen et al., “An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46., No. 1, pp. 63-68, IEEE (Jan. 1999).
Radke et al., “A 14-Bit Current-Mode ΣΔ DAC Based Upon Rotated Data Weighted Averaging,” IEEE Journal of Solid-State Circuits, vol. 35, No. 8, pp. 1074-1084, IEEE (Aug. 2000).
Baird et al., “Improved ΔΣ DAC Linearity Using Data Weighted Averaging”, pp. 13-16, IEEE (1995).
Radke et al., “A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging,” IEEE 1999 Custom Integrated Circuits Conference, pp. 125-128, IEEE (1999).
Jensen et al., “A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 45, No. 1, pp. 13-27, IEEE (Jan. 1998).
Annovazzi et al., A Low-Power 98-dB Multibit Audio DAC in a Standard 3.3-V 0.35-μm CMOS Technology, IEEE Journal of Solid-State Circuits, vol. 37, No. 7, pp. 825-834, IEEE (Jul. 2002).
Weltz et al., “A Necessary and Sufficient Condition for Mismatch Shaping in Multi-Bit DACS,” IEEE, pp. I-105 to I-108, IEEE (2002).
Fogleman et al., “A Digital Common-Mode Rejection Technique for Differential Analog-to-Digital Conversion,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, No. 3, pp. 255-271, IEEE (Mar. 2002).
Lin et al., “A Bandpass Mismatch-Shaped Multi-Bit ΣΔ Switched-Capacitor DAC using Butterfly Shuffler,” 1999 IEEE International Solid-State Circuits Conference, 0-783-5129-0/99, IEEE (1999).
European Search Report from counterpart European application EP 04008879, 3 pp May 8, 2004.

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