Frequency divider with reduced jitter and apparatus based...

Details Frequency divider with reduced jitter and apparatus based... Frequency divider with reduced jitter and apparatus based...

2005-01-11

2005-01-11

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C377S047000

Reexamination Certificate

active

06842054

ABSTRACT:
A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ratio and a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. Further included are a latch for altering the division ratio of each of the frequency dividing cells and D-Flip-Flop circuitry having two latches. A first signal clocks the first latch and a second signal clocks the second latch, whereby the frequency of the first signal is lower than the frequency of the second signal.

REFERENCES:
patent: 4184068 (1980-01-01), Washburn
patent: 4264863 (1981-04-01), Kojima
patent: 5065415 (1991-11-01), Yamashita
patent: 5195111 (1993-03-01), Adachi et al.
patent: 5982840 (1999-11-01), Aisaka
patent: 6066990 (2000-05-01), Genest
patent: 6593782 (2003-07-01), Pierschel et al.

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