Clock circuit with fractional divide circuit

Details Clock circuit with fractional divide circuit Clock circuit with fractional divide circuit

2005-09-27

2005-09-27

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

Reexamination Certificate

active

06950491

ABSTRACT:
A fractional divide circuit for generating a periodic fractional clock is disclosed. A base clock is provided for generating a pre-divide clock at a base clock frequency with a period counter provided for counting cycles of the base clock. A select register stores constants that define parameters for a fractional divide ratio, there being at least four. A positive edge flip flop is provided wherein two of the constants are associated therewith. A negative edge flip flop is provided wherein the other of the two constants are associated therewith. A matching device is operable for setting on the positive edge of the base clock the first flip flop when the first of the two associated constants matches the output of the period counter and clearing the first flip flop when the other of the two associated constants matches the output of the period counter, and setting on the negative edge of the base clock the second flip flop when the first of the two associated constants matches the output of the period counter and clearing the second flip flop when the other of the two associated constants matches the output of the period counter. The outputs of the second and first flip flops are ANDed to provide the fractional clock output.

REFERENCES:
patent: 6459309 (2002-10-01), Canard et al.

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