Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-09-27
2005-09-27
Lam, David (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230080
Reexamination Certificate
active
06950370
ABSTRACT:
A synchronous memory device, receiving a number of data in synchronization with a rising edge and a falling edge of a clock, includes a data strobe buffering unit, a data align latching unit and a DQS signal controlling unit. The data strobe buffering unit outputs a rising pulse and a falling pulse for detecting a rising edge and a falling edge of a DQS signal that sustains a high impedance state when there is no operation and is clocked while the data is inputted. The data align latching unit latches and aligns the data in synchronization with the rising pulse and the falling pulse. The DQS signal controlling unit controls the data strobe buffering unit to output the rising pulse and the falling pulse to the data align latching unit only when the DQS signal is clocked.
REFERENCES:
patent: 6237052 (2001-05-01), Stolowitz
patent: 6320819 (2001-11-01), Tomita et al.
patent: 2003/0128620 (2003-07-01), Nakazato
patent: 01-103016 (1989-04-01), None
patent: 01-276486 (1989-11-01), None
patent: 06-290586 (1994-10-01), None
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Lam David
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