Method for forming reliable MOS devices using silicon rich plasm

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 52, 437 43, 437235, 437238, H01L 2144

Patent

active

056020562

ABSTRACT:
The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

REFERENCES:
patent: 3649884 (1972-03-01), Haneta
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4375125 (1983-03-01), Byatt
patent: 4502202 (1985-03-01), Malhi
patent: 4555300 (1985-11-01), Arnold et al.
patent: 4613888 (1986-09-01), Mase et al.
patent: 4688078 (1987-08-01), Hseih
patent: 4732801 (1988-03-01), Joshi
patent: 4810673 (1989-03-01), Freeman
patent: 4972250 (1990-11-01), Omori et al.
patent: 4996167 (1991-02-01), Chen
patent: 5047829 (1991-09-01), Keller et al.
patent: 5057897 (1991-10-01), Nariani et al.
patent: 5110766 (1992-05-01), Maeda et al.
patent: 5128279 (1992-07-01), Nariani et al.
patent: 5290727 (1994-03-01), Jain et al.
"Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology", by Chen, Min-Liang et al, IEEE Transactions on Electron Devices, vol. 35, No. 12, Dec. 1988, pp. 2210-2220, cited on specification p. 2.
"Mobile Charge in a Novel Spin-On Oxide (SOX): Detection of Hydrogen in Dielectrics", by N. Lefshitz et al, Journal Electrochem. Soc., vol. 136, No. 5, May 1989, pp. 1440-1446, cited on specification p. 3.
"Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-on Glass as the Interlevel Dielectric", by N. Lifshitz et al, IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, pp. 140-142, cited on specification p. 3.
"Field Inversion in CMOS Double Metal Circuits Due to Carbon Based SOGS", by D. Pramanik et al, Proceedings of IEEE VMIC 1989, pp. 454-462, cited on specification pp. 3 and 12.
"Charge Loss in EPROM Due to Ion Generation and Transport in Interlevel Dielectric", by G. Crisenza et al, Proceedings of IEEE IEDM, 1990, pp. 107-110, cited on specification p. 3.
"Electroluminescence Studies in Silicon Dioxide Films Containing Tiny Silicon Islands", by D. J. DiMaria et al, Journal of Appl. Phys., vol. 56, Jul. 1984, pp. 401-416, cited on specification p. 1.
"Improvement of Endurance To Hot Carrier Degradation By Hydrogen Blocking P-SiO", by S. Yoshida et al, IEEE IEDM 1988, pp. 22-25.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming reliable MOS devices using silicon rich plasm does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming reliable MOS devices using silicon rich plasm, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming reliable MOS devices using silicon rich plasm will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-341633

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.