Method of making stacked electrical device having regions of ele

Details Method of making stacked electrical device having regions of ele Method of making stacked electrical device having regions of ele

1995-10-06

1997-02-11

Niebling, John

Fishing, trapping, and vermin destroying

437 60, 437195, 437919, H01L 218242

Patent

active

056020511

ABSTRACT:
An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.

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"A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64Mb DRAMs", Kawamoto et al., 1990 Symposium on VLSI Technology, 13-14, 1990, no month provided.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", Ema et al., IEDM, 592-595 (1988), no month provided.

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