Memory with on-chip detection of bit line leaks

Details Memory with on-chip detection of bit line leaks Memory with on-chip detection of bit line leaks

1995-06-06

1997-02-11

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 43, 437 52, G01R 3126, H01L 2166

Patent

active

056020449

ABSTRACT:
A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which includes a current generator and a means to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit includes a detection circuit.

REFERENCES:
patent: 4800332 (1989-01-01), Hutchins
patent: 4841482 (1989-06-01), Kriefels et al.
patent: 5117394 (1992-05-01), Amin et al.
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5157626 (1992-10-01), Watanabe
patent: 5218570 (1993-06-01), Pascucci et al.
patent: 5241505 (1993-08-01), Hashimoto
patent: 5351214 (1994-09-01), Rouy
patent: 5371706 (1996-12-01), Krentz et al.
"Bit Line Leakage Screen for Directory Chips" IBM Technical Disclosure Bulletin, vol. 33, No. 5, Oct. 1990, pp. 389-390.

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