Multiprocessor cache memory system using temporary access states

Details Multiprocessor cache memory system using temporary access states Multiprocessor cache memory system using temporary access states

1989-05-17

1992-07-14

Shaw, Gareth D.

395425, G06F 1322, G06F 1318

Patent

active

051309220

ABSTRACT:
A store-in cache memory system for a multiprocessor computer system has a status entry in the cache directory which is RO (read-only) when a line of data is read-only, and thus accessible by all processors on the system, or EX (exclusive) when the line accessible for reading or writing but only by one processor. In addition, each directory has an entry, CH, which is set when data in the line is changed. The cache memory system includes two additional statuses, TEX, or temporary exclusive, and TRO, or temporary read-only. When a data fetch instruction results in a cache-miss, and a line containing the requested data is found in a remote cache with an EX status and with its CH bit set, the line is copied to the requesting cache and assigned a status of TEX. The line of data in the remote cache receives a status of TRO. If a store operation for the data occurs within a short time frame, the status in the requesting cache changes to EX and the line in the remote cache is invalidated. Otherwise, the data in the line is castout to main storage and the status of the line becomes RO in both the requesting and remote caches. The addition of these statuses allows the cache system to assign an exclusive status on an anticipatory basis without incurring penalties when this assignment is not appropriate.

REFERENCES:
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4484267 (1984-11-01), Fletcher
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4797814 (1989-01-01), Brenza

Affiliated with

Also associated with

Rating

Multiprocessor cache memory system using temporary access states does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiprocessor cache memory system using temporary access states, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor cache memory system using temporary access states will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-340888