System and method for effective yield loss analysis for...

Details System and method for effective yield loss analysis for... System and method for effective yield loss analysis for...

2005-09-20

2005-09-20

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S110000, C702S084000

Reexamination Certificate

active

06947806

ABSTRACT:
This invention relates to a method for yield loss analysis of process steps of semiconductor wafers having a plurality of dies, and more particularly relates to a defect inspection technique to determine a hit ratio, computation of yield impact contributions for the defects, and determination of a kill ratio for a specific type of defect. Yield loss is estimated ultimately upon a choice of a defect density distribution function. A defect calibrated factor and a yield impact calibrated factor are introduced herein.

REFERENCES:
patent: 6367040 (2002-04-01), Ott et al.
patent: 6496958 (2002-12-01), Ott et al.
patent: 6613590 (2003-09-01), Simmons
patent: 6717431 (2004-04-01), Rathei et al.
patent: 2002/0002415 (2002-01-01), Mugibayashi et al.
Patterson, O.D., Hansen, M.H., “The impact of tolerance on kill ratio estimation for memory”, Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI , Sep. 12-14, 2000, pp.: 175-180.

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