Regionally time multiplexed emulation system

Details Regionally time multiplexed emulation system Regionally time multiplexed emulation system

2005-09-20

2005-09-20

Thomson, B. D. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S027000, C703S024000

Reexamination Certificate

active

06947882

ABSTRACT:
A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 5036473 (1991-07-01), Butts et al.
patent: 5363319 (1994-11-01), Okuda
patent: 5574388 (1996-11-01), Barbier et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 5659716 (1997-08-01), Selvidge et al.
patent: 5701441 (1997-12-01), Trimberger
patent: 5761484 (1998-06-01), Agarwal et al.
patent: 5777489 (1998-07-01), Barbier et al.
patent: 5847578 (1998-12-01), Noakes et al.
patent: 5854752 (1998-12-01), Agarwal
patent: 5920712 (1999-07-01), Kuijsten
patent: 5960191 (1999-09-01), Sample et al.
patent: WO 94/06210 (1994-03-01), None
patent: WO 94/23389 (1994-10-01), None
Shibata, Y.; Miyazaki, H.; Xiao-Ping Ling; Amano, H., Towards the realistic “virtual hardware,” Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997, 1998 pp.: 50-55.
Varghese, J.; Butts, M.; Batcheller, J., “An efficient logic emulation system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.: 1 Issue: 2, Jun. 1993 pp.: 171-174.
Lo, W.Y.; Choy, C.S.; Chan, C.F., “Hardware emulation board based on FPGAs and Programmable Interconnections,” Proceedings of the Fifth International Workshop on Rapid System Prototyping, 1994. Shortening the Path from Spec to Prototype. pp.: 126-130.
Babb, et al., “Logic Emulation with Virtual Wires,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 6, Jun. 1997, pp. 609-626.
Berger, “Teramac HW Simulator System External Reference Specification,” Nov. 7, 1991, Revision 1.1, pp. 3-37.
Snider et al., “The PLASMA Chip Specification,”Aug. 1, 1995, pp. 1-124.
Snider et al., “The Teramac Configurable Compute Engine,” Field Programmable Logic and Applications, 5thInternational Workshop, FPL '95 Oxford, United Kingdom, pp. 44-53.
XILINX, “The Programmable Gate Array Design Handbook,” First Edition, 1986, pp. i-A-10.
“Translation of an Office Action of Japanese Patent Office,” from a Japanese counterpart application, 7 pgs., Jul. 2, 2002.
Office Action of Japanese Patent Office, from the Japanese counterpart application, 6 pgs., Jul. 2, 2002.

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