Instruction register and access port gated clock for scan cells

Details Instruction register and access port gated clock for scan cells Instruction register and access port gated clock for scan cells

2005-05-24

2005-05-24

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C438S005000

Reexamination Certificate

active

06898544

ABSTRACT:
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

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