Multi step electrodeposition process for reducing defects...

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area

Reexamination Certificate

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C205S117000, C205S123000, C205S137000, C205S223000, C438S675000, C438S687000

Reexamination Certificate

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06946066

ABSTRACT:
The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.

REFERENCES:
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patent: 6709970 (2004-03-01), Park et al.
patent: 6750144 (2004-06-01), Taylor
patent: 2003/0015435 (2003-01-01), Volodarsky et al.
patent: 2003/0119311 (2003-06-01), Basol et al.
patent: 2004/0012090 (2004-01-01), Basol et al.
patent: 2000208443 (2000-07-01), None
patent: WO 01/32362 (2001-05-01), None
Reid et al., “Factors influencing damascene feature fill using copper PVD and electroplating,”Solid State Technology, Jul. 2000, pp. 86-103.

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