Semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S203000, C365S226000

Reexamination Certificate

active

06847579

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.

REFERENCES:
patent: 5604712 (1997-02-01), Priebe
patent: 5825714 (1998-10-01), Kohno
patent: 6044035 (2000-03-01), Kohno
patent: 6075746 (2000-06-01), Ohsawa
patent: 6088289 (2000-07-01), Landry et al.
patent: 6115319 (2000-09-01), Kinoshita et al.
patent: 9-161483 (1997-06-01), None
patent: 11-66840 (1999-03-01), None
patent: 1994-0012392 (1994-06-01), None
patent: 10-0211482 (1999-05-01), None

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