Frequency divider system

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S113000, C327S115000

Reexamination Certificate

active

06847239

ABSTRACT:
A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.

REFERENCES:
patent: 3873815 (1975-03-01), Summers
patent: 3896387 (1975-07-01), Kokado
patent: 3943379 (1976-03-01), McGuffin
patent: 4366394 (1982-12-01), Clendening et al.
R. Magoon, et al., “RF Local Oscillator Path for GSM Direct Conversion Transceiver with True 50% Duty Cycle Divide by Three and Active Third Harmonic Cancellation,” 2002 IEEE Radio Frequency Integrated Circuits Symposium, pp. 23-26.

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