System and method for reducing trapped charge effects in a...

Details System and method for reducing trapped charge effects in a... System and method for reducing trapped charge effects in a...

2005-07-05

2005-07-05

Le, Que T. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S2140RC

Reexamination Certificate

active

06914230

ABSTRACT:
A system and method for reducing image lag in a complementary metal oxide semiconductor (CMOS) photodetector is disclosed. In one embodiment, the invention is a a method for reducing image lag in an array of complementary metal oxide semiconductor (CMOS) photodetectors by forward biasing the photodetectors during a first time period to charge charge traps in the photodetectors, and reverse biasing the photodetectors during a second time period to remove charge from the photodetectors except the charge trapped in the charge traps.

REFERENCES:
patent: 3727076 (1973-04-01), Mar

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