Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2005-04-05
2005-04-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S106000, C438S112000, C438S118000, C438S123000, C438S124000, C438S082000, C438S099000, C438S778000, C438S780000, C438S781000, C438S782000, C257S040000, C257S666000, C257S678000, C257S687000
Reexamination Certificate
active
06875640
ABSTRACT:
A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.
REFERENCES:
patent: 3428503 (1969-02-01), Beckerle
patent: 4575330 (1986-03-01), Hull
patent: 4752498 (1988-06-01), Fudim
patent: 4945032 (1990-07-01), Murphy et al.
patent: 5041695 (1991-08-01), Olenick et al.
patent: 5059021 (1991-10-01), Spence et al.
patent: 5088047 (1992-02-01), Bynum
patent: 5149958 (1992-09-01), Hallenbeck et al.
patent: 5164128 (1992-11-01), Modrek et al.
patent: 5173220 (1992-12-01), Reiff et al.
patent: 5185210 (1993-02-01), Zupancic
patent: 5227232 (1993-07-01), Lim
patent: 5250843 (1993-10-01), Eichelberger
patent: 5264061 (1993-11-01), Juskey et al.
patent: 5278442 (1994-01-01), Prinz et al.
patent: 5299091 (1994-03-01), Hoshi et al.
patent: 5355016 (1994-10-01), Swirbel et al.
patent: 5418189 (1995-05-01), Heinen
patent: 5484314 (1996-01-01), Farnworth
patent: 5512710 (1996-04-01), Schroeder
patent: 5545367 (1996-08-01), Bae et al.
patent: 5648127 (1997-07-01), Turchan et al.
patent: 5705117 (1998-01-01), O'Connor et al.
patent: 5897338 (1999-04-01), Kaldenberg
patent: 5900346 (1999-05-01), Sinta et al.
patent: 5943235 (1999-08-01), Earl et al.
patent: 5945058 (1999-08-01), Manners et al.
patent: 5945130 (1999-08-01), Saxelby, Jr. et al.
patent: 5946556 (1999-08-01), Hashizume
patent: 5987739 (1999-11-01), Lake
patent: 6025114 (2000-02-01), Popat et al.
patent: 6045655 (2000-04-01), DiStefano et al.
patent: 6056191 (2000-05-01), Brouillette et al.
patent: 6215095 (2001-04-01), Partanen et al.
patent: 6229204 (2001-05-01), Hembree
patent: 6242932 (2001-06-01), Hembree
patent: 6251488 (2001-06-01), Miller et al.
patent: 6253116 (2001-06-01), Zhang et al.
patent: 6259962 (2001-07-01), Gothait
patent: 6263566 (2001-07-01), Hembree et al.
patent: 6268584 (2001-07-01), Keicher et al.
patent: 6268655 (2001-07-01), Farnworth et al.
patent: 6284563 (2001-09-01), Fjelstad
patent: 6326698 (2001-12-01), Akram
patent: 6337122 (2002-01-01), Grigg et al.
patent: 6391251 (2002-05-01), Keicher et al.
patent: 6432752 (2002-08-01), Farnworth
patent: 6482576 (2002-11-01), Farnworth et al.
patent: 6489007 (2002-12-01), Grigg et al.
patent: 6514798 (2003-02-01), Farnworth
patent: 6524346 (2003-02-01), Farnworth
patent: 6544821 (2003-04-01), Akram
patent: 6544902 (2003-04-01), Farnworth
patent: 6549821 (2003-04-01), Farnworth et al.
patent: 6562278 (2003-05-01), Farnworth et al.
patent: 6585927 (2003-07-01), Grigg et al.
patent: 6593171 (2003-07-01), Farnworth
patent: 6621154 (2003-09-01), Satoh et al.
patent: 6635333 (2003-10-01), Grigg et al.
patent: 20010051391 (2001-12-01), Williams
patent: 20020066966 (2002-06-01), Farnworth
patent: 20020098623 (2002-07-01), Akram
patent: 20020171177 (2002-11-01), Kritchman et al.
patent: 20020182782 (2002-12-01), Farnworth
patent: 20030003180 (2003-01-01), Farnworth et al.
patent: 20030003380 (2003-01-01), Farnworth et al.
patent: 20030003405 (2003-01-01), Farnworth et al.
patent: 20030043360 (2003-03-01), Farnworth
patent: 20030068584 (2003-04-01), Farnworth et al.
patent: 20030072926 (2003-04-01), Grigg et al.
patent: 20030077418 (2003-04-01), Grigg et al.
patent: 20030089999 (2003-05-01), Akram
patent: 20030092220 (2003-05-01), Akram
patent: 20030093173 (2003-05-01), Farnworth
patent: 20030102566 (2003-06-01), Farnworth
patent: 20030129787 (2003-07-01), Farnworth
patent: 20030151167 (2003-08-01), Kritchman et al.
patent: 20030203158 (2003-10-01), Farnworth et al.
patent: 20040104486 (2004-06-01), Boon
patent: 0322257 a3 (1988-12-01), None
Miller et al., “Maskless Mesoscale Materials Deposition”, Deposition Technology, Sep. 2001, pp. 20-22.
Miller, “New Laser-Directed Deposition Technology”, Microelectronic Fabrication, Aug. 2001, p. 16.
Webpage, Objet Prototyping the Future, “Objet FullCure700 Series”, 1 page.
Wepage, Objet Prototyping the Future, “How it Works”, 2 pages.
U.S. Appl. No. 09/651,930, filed Aug. 31, 2000, entitled “Semiconductor Device Including Leads in Communication with Contact Pads Thereof and a Stereolithographically Fabricated Package Substantially Encapsulating the Leads and Methods for Fabricating the Same”, inventor Salman Akram.
U.S. Appl. No. 10/370,755, filed Feb. 20, 2003, entitled “Chip Scale Package Structures and Method of Forming Conductive Bumps Thereon”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/455,091, filed Jun. 5, 2003, entitled “Methods for Stereolithographic Processing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/608,749, filed Jun. 26, 2003, entitled “Methods for Labeling Semiconductor Device Components”, inventor Grigg et al.
U.S. Appl. No. 10/619,918, filed Jul. 15, 2003, entitled “Stereolithographic Methods for Fabricatin Hermetic Semiconductor Device Packages and Semiconductor Devices Including Stereolithographically Fabricated Hermetic Packages”, inventor Warren M. Farnworth.
U.S. Appl. No.10/672,098, filed Sep. 26, 2003, entitled “Apparatus and Methods for Use in Stereolithographic Processing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/690,417, file Oct. 20, 2003, entitled “Methods of Coating and Singulating Wafers and Chip-Scale Packages Formed Therefrom”, inventor Farnworth et al.
Farnworth Warren M.
Wood Alan G.
Lee Jr. Granvill D
Smith Matthew
TraskBritt
LandOfFree
Stereolithographic methods for forming a protective layer on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stereolithographic methods for forming a protective layer on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stereolithographic methods for forming a protective layer on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3379460