Hard phase alignment of clock signals using asynchronous...

Details Hard phase alignment of clock signals using asynchronous... Hard phase alignment of clock signals using asynchronous...

2005-01-04

2005-01-04

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000

Reexamination Certificate

active

06838918

ABSTRACT:
A frequency synthesizer for a programmable logic device includes a phase alignment circuit that is controlled by an asynchronous level-mode state machine. The state machine receives a start signal generated by the circuits that determine a concurrence cycle when reference and generated clock signals should be aligned. Then, at the concurrence cycle the state machine replaces a generated clock edge with a reference clock edge to bring the generated clock signal into hard phase alignment with the reference clock signal.

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U.S. patent application Ser. No. 09/684,529, Logue et al., filed Oct. 6, 2000.

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