Minimal latency serial media independent interface to media...

Details Minimal latency serial media independent interface to media... Minimal latency serial media independent interface to media...

2005-03-08

2005-03-08

Ton, Dang (Department: 2666)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C370S503000, C375S354000

Reexamination Certificate

active

06865189

ABSTRACT:
A method for reducing latency in conversions from a SMII (Serial Media Independent Interface) to a MII (Media Independent Interface). The method involves generating receive and transmit clock signals from a physical layer device; generating receive and transmit clock signals at a media access controller; and synchronizing the clock signals at the media access controller and the clock signals at the physical layer device such that MII clocks are generated from the SMII and a synchronization signal of the SMII is always delayed 8 nsec from a positive edge of the MII clock.

REFERENCES:
patent: 20020126684 (2002-09-01), Findlater et al.
patent: 20030061341 (2003-03-01), Loh et al.
patent: 20030099253 (2003-05-01), Kim
Intel Development Kit Manual, “LXD9785 PQFP Demo Board with FPGA for RMII-to-MII Conversion”, Jan. 24, 2002.

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