Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-24
2004-06-08
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C377S074000, C377S079000
Reexamination Certificate
active
06747627
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a shift register circuit constructed by thin film transistor (TFTs), in particular, a redundancy shift register circuit.
A shift register circuit in which TFTs are used is utilized in a driver circuit of an image sensor or a liquid crystal display (LCD) device, in particular, recently, in a driver circuit of an active matrix type display device.
In an active matrix type display device, each pixel is arranged in a cross section portion of an active matrix circuit and connected with a switching element, and image information is controlled by on/off of the switching element. As a display media of such display device, a liquid crystal, plasma, an object (state) capable of electrically changing an optical characteristic (reflectance, refractive index, transmimissivity, emission (luminous) strength) or the like are used. As a switching element, in particular, a three terminal element, that is, a field effect transistor having a gate, a source and a drain is used.
In a matrix circuit, a signal line (a gate line) which is arranged in parallel to a line is connected with gate electrodes of transistors with respect to the line, and a signal line (a source line) which is arranged in parallel to a column is connected with source (or drain) electrodes of the transistors with respect to the column. A circuit for driving the gate line is referred to as a gate driver circuit, and a circuit for driving the source line is referred to as a source driver circuit.
Since the gate driver circuit generates a vertical line scan timing signal with respect to an active matrix type display device, a shift register includes serial-connected registers (in a single line) corresponding to the number of gate lines with a vertical direction. As a result, switching of thin film transistors (TFTs) in an active matrix type display device is performed by the gate driver circuit.
Since the source driver circuit generates a horizontal line image signal of image data to be displayed on an active matrix type display device, a shift register includes serial-connected registers (in a single line) corresponding to the number of source lines with a horizontal direction. Also, by a latch pulse synchronous with a horizontal scan signal, an analog switch is turned on or off. As a result, a current is supplied from the source driver circuit to TFTs in an active matrix type display device, to control alignment of a liquid crystal cell.
Referring to
FIG. 5
, a common active matrix type display device will be described.
A horizontal line scan timing signal is generated by a shift register
51
. Analog switches
53
and
54
are turned on and then a video signal is stored in analog memories
55
and
56
in response to the horizontal line scan timing signal. Image data corresponding to the video signal stored in the analog memories
55
and
56
is stored in analog memories
59
and
60
through analog switches
57
and
58
turned on by timing of a latch pulse. The image data is supplied from the analog buffers
59
and
60
to source lines of TFTs
63
and
64
through analog buffers
61
and
62
in an active matrix circuit
70
of an active matrix type liquid crystal display device in timing of the latch pulse.
On the other hand, a vertical line scan timing signal is generated by a shift register
52
and then supplied to gate lines of the TFTs
63
and
64
in the active matrix circuit
70
of the active matrix type liquid crystal display device.
Therefore, the image data (voltage) supplied to the source lines is applied to liquid crystals
65
and
66
, to determine alignment of the liquid crystals
65
and
66
connected with drain lines of the TFTs
63
and
64
, the active matrix type liquid crystal display device is operated by the above operation.
Generally, a shift register includes a circuit as shown in
FIGS. 6A and 6B
, in particular, a D-type flip-flop.
FIG. 6A
shows a D-type flip-flop constructed using analog switches, and
FIG. 6B
shows a D-type flip-flop constructed using clocked invertors. These operation will be described below.
In
FIG. 6A
, when an operation clock CK is a high level (H) and an input signal DATA is a high level (H), a complementary type transmission gate a-
1
is turned on and then the input signal DATA is input to a complementary type invertor circuit a-
2
. Therefore, an output of the complementary type invertor circuit a-
2
becomes a low level (L). In this state, complementary type transmission gates a-
4
and a-
5
are in a turn off state.
When the operation clock CK is changed to a low level (L) while the input signal DATA is a high level (H), the complementary transmission gate a-
1
becomes a turn off state, the complementary type transmission gates a-
4
and a-
5
become a turn on state. Therefore, an output of the complementary invertor circuit a-
2
is held to a low level (L).
Also, since the complementary type transmission gate a-
5
becomes a turn on state, an output of an complementary type invertor circuit a-
6
becomes a high level (H). In this state, a complementary type transmission gate a-
8
becomes a turn off state.
When the operation clock CK is changed to a high level (H) again, the complementary transmission gate a-
5
becomes a turn off state and the complementary type transmission gate a-
8
becomes a turn on state, so that a previous signal level is held. Therefore, an output of the complementary type invertor circuit a-
6
can be held to an input signal DATA having a high level (H) in synchronous with an operation clock CK.
As a result, a D-type flip-flop can be constructed using transmission gates. Also, when an input signal DATA is a low level (L), the above described operation is performed.
In
FIG. 6B
, when the operation clock CK is a high level (H) and the input signal DATA is a high level (H), an output of a complementary clocked invertor circuit b-
1
becomes a low level (L) and then an output of the complementary invertor circuit b-
2
becomes a high level (H). In this state, complementary clocked invertor circuits b-
3
and b-
4
are in a turn off state.
When the operation clock CK is changed to a low level (L) while the input signal DATA is a high level (H), the complementary clocked invertor circuits b-
3
and b-
4
are turned on, so that an output of the complementary type invertor circuit b-
2
is held to a high level (H). An output of the complementary invertor circuit b-
5
becomes a high level (H). In this state, the complementary clocked invertor circuit b-
6
is a turn off state.
When the operation clock CK is changed to a high level again, the complementary type clocked invertor circuit becomes a turn off state, and the complementary type clocked invertor circuit becomes a turn on state. Therefore, an output of the complementary type invertor circuit can be held to an input signal DATA having a high level (H) in synchronous with an operation clock CK.
As a result, a D-type flip-flop is constructed by clocked invertors. Also, when an input signal DA,A is a low level (L), the above described operation is performed.
In a shift register circuit used in gate and source driving circuits of a common active matrix type display device, as shown in
FIGS. 2A and 2B
, registers having the same number as the number of gate lines (or source lines) are connected in serial. In a gate driver circuit as shown in
FIG. 2A
, outputs of registers SR
i
(i=1 to n) in a shift register circuit
120
are connected to gate lines
123
and
124
through invertor type buffer circuits
121
and
122
. In a source driver circuit as shown in
FIG. 2B
, outputs of registers SR
i
(i=1 to N) in a shift register circuit
125
are connected to control terminals of sampling transmission gates
128
and
129
through invertor type buffer circuits
126
and
127
.
If at least one register has defect an the shift register circuit having serial-connected registers, image data and scan timing signals output from the defect register and later connected register are abnormal, an accuracy image cannot be obt
Kawasaki Yuji
Koyama Jun
Bell Paul A.
Costellia Jeffrey L.
Nixon & Peabody LLP
Saras Steven
Semiconductor Energy Laboratory Co,. Ltd.
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