Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
2000-01-03
2004-06-08
Dharia, Rupal (Department: 2141)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S211000, C709S212000, C709S216000, C709S236000, C709S237000, C370S230000, C370S439000, C370S473000, C370S474000, C370S476000, C370S520000, C710S029000, C710S061000, C710S105000, C712S214000, C712S220000, C712S233000
Reexamination Certificate
active
06748442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to packet based communication links and more particularly to use of a control signal to send control related information over the link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG.
1
. One feature of this prior art architecture is the use of the Peripheral Component Interconnect (PCI) bus
101
as the connection between the “north bridge” integrated circuit
103
and the “south bridge” integrated circuit
105
. The north bridge functions generally as a switch connecting CPU
107
, a graphics bus
109
such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory
111
. The north bridge also contains the memory controller function. The architecture also includes the “host bus” connection
108
between north bridge
103
and processor
107
.
The south bridge
105
provides an interface to various input/output (I/O) portions of the computer system by providing a bridge function between the PCI and legacy ISA bus
115
, the Integrated Device Electronics (IDE) disk interface
117
and the Universal Serial Bus (USB)
119
. Other devices, buses and functions may also be included in the South Bridge
105
. In the illustrated prior art architecture, PCI bus
101
also functions as a major input/output bus for add-in functions such as network connection
121
. The various busses and devices shown in
FIG. 1
are conventional in the personal computer industry and are not described further herein.
Demand for increased system performance and the continuing increase in processor speeds puts pressure on system buses such as the PCI bus and the host bus to also provide better performance. However, configuration of some of the present buses, such as the multi-drop configuration of the PCI bus, tends to limit its performance.
One type of information that needs to be transferred between the various components in the computer system is a variety of control information. Such control information may relate to a particular transfer on the interconnection such as the type of transfer taking place, may indicate a target address for an operation or may relate to such system information as configuration, interrupts or power management. As levels of integration increase and more functions are integrated into fewer components, more functions must send information over the same interconnect. As a result, there is a danger that latency of certain control information can become unacceptably long. Further, given the continually increasing speeds of processors and other system components, latencies that were previously acceptable may have become unacceptable.
Thus, it would be desirable to have a high speed interconnect providing improved quality of service for the various components of the computer system. It would also be desirable that such an interconnect address potential latency issues that may be related to transmission of control information.
SUMMARY OF THE INVENTION
Accordingly, the invention allows a control packet with potentially higher priority control information to be inserted into the middle of a data packet. After completing transfer of the inserted control packet, transfer of the interrupted data packet then resumes at the point that it left off.
In one embodiment the invention provides a method of operating a computer system. The method includes transferring at least a first byte of a data packet having multiple bytes, from a first node to a second node of a communication link. The communication link includes a control signal, which is asserted during transfer of the data packet, before all of the bytes of the data packet have been transferred. Transfer of the data packet is then suspended in synchronism with asserting the control signal. After the suspension, a control packet, which includes a command field, is transferred with the control signal asserted. After transferring the control packet, the control signal is again deasserted and transfer of the data packet resumes at the point where it was suspended.
In another embodiment the invention provides an integrated circuit that includes a plurality of terminals for coupling to a communication link. The integrated circuit includes terminals for a first data portion of the communication link and for a first control line of the communication link. The integrated circuit also includes control logic coupled to supply the first data portion with a first control packet and to supply the first data portion with a data packet of multiple bytes associated with the first control packet. The control logic is responsive to availability of a second control packet to suspend transfer of the first data packet, insert the second control packet on the first data portion and then resume transfer of the data packet on completion of transferring the second control packet. The control line indicates whether the packet being transferred is a control packet or a data packet.
In another embodiment, a computer system is provided that includes a first node, a second node and a communication link connecting the first and second nodes. The communication link includes a first data portion and a first control line. The first data portion carries data packets of multiple bytes and control packets from the first to the second node. The first control line is at a first value during transfer of the control packets and at a second value during transfer of the data packets. Control logic in the first node is responsive to suspend transfer of one of the data packets and to place the control line at the first value to indicate the suspension. The control logic then inserts a control packet onto the first data portion and resumes the data packet transfer on completion of the transfer of the inserted control packet.
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patent
Dharia Rupal
Pollack Melvin H.
Zagorin O'Brien & Graham LLP
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