Television – Synchronization – Locking of video or audio to reference timebase
Reexamination Certificate
2001-01-05
2004-06-29
Kostak, Victor R. (Department: 2611)
Television
Synchronization
Locking of video or audio to reference timebase
C348S500000, C375S371000
Reexamination Certificate
active
06757024
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing recovery technique, and more particularly, to a timing recovery apparatus and method for a digital TV using the envelope of a timing error calculated according to a channel state.
2. Description of the Background Art
With respect to data transmission of a transmitter in a digital communication apparatus, if a receiver performs sampling at a high or low speed, it reads another value after the sampling, thereby causing an error. Thus, the timing for the transmission rate, transmission time, and interval of each bit at the transmitter side must be the same as the receiver side. That is, in the digital communication apparatus, an output of a demodulator has to be periodically sampled with perfect timing according to a symbol rate to thus be read. In order to perform such a periodical sampling, the receiver receives a clock signal request. This step of extracting a clock signal from the receiver is called as a symbol timing recovery.
The symbol timing recovery can be performed in many ways. In general, a clock used by the transmitter is transmitted along with a data signal. At that time, the timing recovery is easy, but an additional in-frequency band for transmitting clocks are required and a large amount of power is needed. In addition, in a digital TV using a transmission specification of a vestigial sideband transmission system, there is no additional in-clock transmission, and accordingly self-synchronization method for extracting a clock signal from a received signal.
FIG. 1
is a block diagram illustrating a general QAM demodulator. As illustrated therein, the QAM modulator includes: a sampling unit
1
for sampling an input signal by a sampling clock; a multiplier
2
for multiplying an output signal of the sampling unit
1
by a signal of a predetermined frequency outputted from a numerical control oscillator
5
to thus output a baseband signal; a signal processing unit
3
for performing signal processing such as matched filtering upon receipt of the baseband signal outputted from the multiplier
2
; a carrier synchronization and channel equalizer
4
for compensating the distortion of the signal outputted from the baseband signal processing unit
3
; a numerical control oscillator
5
for outputting a signal of a frequency in order to obtain an accurate baseband signal according to an error detected by the carrier synchronization and channel equalizer
4
; a symbol synchronization unit
6
for estimating a proper symbol transition point from the signal inputted from the baseband signal processing unit
3
; and a lock detector
7
for detecting a convergence state of the symbol synchronization unit to thus adjust a bandwidth.
Here, the symbol synchronization unit
6
is generally disposed at the front end of a digital receiver, and transfers symbol data synchronized with the symbol to the carrier synchronization and channel equalizer
4
at the rear end. Thus, in order to improve the convergence characteristic of the symbol synchronization unit
6
, a high-speed initial synchronization acquisition and a low jitter characteristic in steady state are required. To acquire initial synchronization at a higher speed, the loop bandwidth of a timing recovery loop has to be larger. On the contrary, to obtain a low jitter characteristic in the steady state, the loop bandwidth of the timing recovery loop has to be smaller.
A method of acquiring synchronization by increasing the loop bandwidth of the timing recovery loop at an initial period, and improving a jitter characteristic by decreasing the loop bandwidth, if it is judged that the jitter characteristic is converged to the steady state by the lock detector
7
, is called as “gear shifting”. In addition, to acquire a rapid and accurate convergence characteristic of the receiver more in engagement with a carrier synchronization unit, information on the convergence state of the timing recovery loop is required. Therefore, the lock detector
7
needs an accurate sensing ability necessary to improve and stabilize the performance of the receiver.
The operation of a conventional symbol synchronization unit and lock detector will now be described with reference to
FIGS. 1 and 2
.
FIG. 2
is a block diagram illustrating the algorithm principle of a conventional timing lock detector. In the symbol synchronization unit
10
, a timing error detector
11
calculates an error from a baseband signal, this error being accumulated on an integrator of a loop filter
12
to control a numerical control oscillator or a voltage control oscillator
13
, thereby recovering symbol synchronization. At this time, as illustrated in
FIG. 1
, since the bandwidth of the timing recovery loop consisting of the sampling unit
1
and the synchronization unit
6
is proportional to the gain of a close loop, the loop bandwidth can be controlled by gradually adjusting the gain of the close loop using the timing lock detector
20
. In other words, the timing lock detector
20
obtains a variance
21
of an error(X) accumulated on the integrator of the loop filter
12
, and compares the variance
21
with a fixed threshold
22
, thereby judging a locking point. A lock signal is delivered from the comparator
23
to a lock controller
24
, thereby selecting the loop bandwidth of the close loop.
FIGS. 3A and 3B
are graphs illustrating an algorithm principle of a conventional lock detector. In
FIG. 3A
, the error(X) accumulated on the integrator of the loop filter is converged according to a channel state(SNR), and thereafter the magnitude of a residual jitter becomes inversely proportional to the channel state(SNR) in the steady state. Thus, the variance of the error(X) varies according to the channel state. Therefore, since the hardware cost for calculating the variance is very large, and the variance varies according to the channel state after convergence, the fixed threshold causes the generation of a wrong lock signal, which results in a lock error. With such a lock error, it is made impossible for a large timing frequency and phase offset to be converged, as well as convergence time is lengthened. In addition, although an appropriate threshold can be obtained by using a SNR calculator, the hardware cost for the SNR calculator is increased, and the convergence time of the symbol synchronization unit is lengthened as much as the calculation time of the SNR calculator. Hence, it is impossible to have a high-speed synchronization acquisition convergence characteristic, though it is possible to have a low residual jitter characteristic, thus making it difficult to exhibit the performance of the lock detector.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a timing recovery apparatus and method for a digital TV by using not a fixed reference value(REF), but the envelope of a timing error calculated according to a channel state(SNR) as a reference value.
It is another object of the present invention to provide a timing recovery apparatus and method for a digital TV in which a timing lock detector performs timing recovery by itself, minimizes the effect between a carrier synchronization recovery and itself in engagement with the carrier synchronization unit, and prevents a lock error.
It is another object of the present invention to provide a timing recovery apparatus and method for a digital TV in which a single lock detector is capable of gradually selecting a loop bandwidth appropriated for a channel state by having a lock counter and an unlock counter.
To achieve the above objects, there is provided a timing recovery apparatus and method for a digital TV according to the present invention, which includes: a symbol synchronization unit for determining the bandwidth of a timing recovery loop in a plurality of steps according to a convergence degree to output a sampling frequency upon receipt of a baseband signal; and a timing lock detector for detecting the convergence state of the symbol synchronization unit and detecting a lo
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