Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2003-03-11
2004-06-01
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
C438S197000, C438S680000
Reexamination Certificate
active
06743692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a self-alignment contact structure utilizing a selective epitaxial growth method.
2. Description of the Background Art
With an increase in a degree of integration of a semiconductor device, a wiring width has been reduced and a space width between wirings has also been decreased gradually. In order to form a contact hole to penetrate between the wirings, accordingly, a much finer pattern than the space width between the wirings in such a situation has been required.
In consideration of an overlay accuracy (=&agr;) and a dimensional accuracy (=&bgr;) of a photolithographic process, C>0.25−f (&agr;, &bgr;) &mgr;m is required for a size C of a contact hole required in a design rule in which the space width between the wirings is set to be 0.25 &mgr;m. With an increase in the degree of integration of the semiconductor device, the size C of the contact hole exceeds the limit of microfabrication determined by a wavelength of a light source of an exposing device. f (&agr;, &bgr;) is a function setting a and &bgr; to be variables.
In order to solve such a problem, a self-alignment contact technique has been utilized at the time of the manufacture of the semiconductor device having a 0.25 &mgr;m rule.
In a DRAM (Dynamic Random Access Memory), the self-alignment contact technique is used most often in forming a bit line contact and a storage node contact which are formed between word lines in a memory cell array. In this case, it is important that a source/drain region of a memory cell transistor, and a bit line and a storage node are to be connected with a low resistance in any way without an electrical short circuit with a word line. The “bit line contact” indicates a contact plug to be connected to a bit line and the “storage node contact” indicates a contact plug to be connected to a storage node of a DRAM capacitor.
With reference to
FIG. 29
, description will be given to a method of manufacturing a conventional semiconductor device in which the self-alignment contact technique is used.
FIG. 29
is a sectional view showing a structure of the conventional semiconductor device. The semiconductor device shown in
FIG. 29
has a memory cell of a DRAM, for example, and
FIG. 29
shows a part thereof.
Referring to
FIG. 29
, in the method of manufacturing the conventional semiconductor device, an element isolation insulating film
105
formed of a silicon oxide film is first formed in a main surface of a semiconductor substrate
101
, for example. Then, a p-type well region
108
to be a p-type impurity region is formed in the main surface of the semiconductor substrate
101
divided by the element isolation insulating film
105
.
Next, a plurality of gate structures
160
and a plurality of source/drain regions
113
a
and
113
b
are formed. In the gate structure
160
, a gate insulating film
109
, a gate electrode
150
to be a word line and a cap film
112
are provided on the p-type well region
108
in this order. The gate electrode
150
has such a structure that a polysilicon film
110
, a buffer film which is not shown and a metal film
111
are provided in this order.
The gate insulating film
109
is formed by a silicon oxide film, for example, and the cap film
112
is formed by a silicon nitride film, for example. Moreover, the buffer film of the gate electrode
150
is formed of WSiN, for example, and the metal film
11
is formed of tungsten (W), for example.
The source/drain regions
113
a
and
113
b
are n-type impurity regions respectively and are formed in an upper surface of the p-type well region
108
at a predetermined distance. More specifically, the source/drain regions
113
a
and
113
b
are formed in the upper surface of the p-type well region
108
interposed between the gate structures
160
which are adjacent to each other.
Next, a sidewall insulating film
117
formed of a silicon nitride film is formed on a side surface of the gate structure
160
, for example. By using a selective epitaxial growth method, then, epitaxial layers
119
a
and
119
b
are formed in self-alignment on the source/drain regions
113
a
and
113
b
, respectively.
Thereafter, a silicide layer which is not shown is formed on only upper surfaces of the epitaxial layers
119
a
and
119
b
. More specifically, a titanium (Ti) film is first formed on a whole surface by sputtering and a heat treatment is successively carried out. Consequently, silicon reacts to Ti so that siliciding is carried out. By removing an unreacted titanium film, subsequently, a silicide layer is formed on only the upper surfaces of the epitaxial layers
119
a
and
119
b.
Next, a space between the gate structures
160
is filled and an interlayer insulating film
121
is formed over a whole surface. Then, an upper surface of the interlayer insulating film
121
is flattened. The interlayer insulating film
121
is formed by a silicon oxide film containing an impurity such as boron and phosphorus. Thereafter, a resist having a predetermined opening pattern is formed on the interlayer insulating film
121
and the interlayer insulating film
121
is selectively etched. Consequently, a contact hole
130
a
reaching the silicide layer provided on the epitaxial layer
119
a
and a contact hole
130
b
reaching the silicide layer provided on the epitaxial layer
119
b
are formed. When the interlayer insulating film
121
is to be etched, the sidewall insulating film
117
and the cap film
112
in the gate structure
160
function as etching stoppers. Therefore, the gate electrode
150
is not exposed and the contact holes
130
a
and
130
b
are formed in self-alignment.
Next, a contact plug
122
a
for filling in the contact hole
130
a
and a contact plug
122
b
for filling in the contact hole
130
b
are formed. Each of the contact plugs
122
a
and
122
b
is formed by a polysilicon film, for example. Then, an electrical connection to the contact plug
122
b
is carried out to provide a bit line which is not shown. Consequently, the bit line and the source/drain region
113
b
are electrically connected to each other through the contact plug
122
b
and the epitaxial layer
119
b.
Moreover, an electrical connection to the contact plug
122
a
is carried out to provide a storage node of a DRAM capacitor which is not shown. Consequently, the storage node of the capacitor and the source/drain region
113
a
are electrically connected to each other through the contact plug
122
a
and the epitaxial layer
119
a
. Then, a dielectric film and an upper electrode in the capacitor are provided.
Prior art document information related to a semiconductor device using a self-alignment contact technique includes patent documents 1 (Japanese Patent Application Laid-Open No. 6-37272 (1994)) and 2 (Japanese Patent Application Laid-Open No. 2001-44382). Moreover, prior art document information related to a semiconductor device using a selective epitaxial growth method includes a non-patent document 1 (Hideaki Matsuhashi and three others, “Development of 0.15 &mgr;m Gate Length SOI COMS Transistor using Elevated Source/Drain”, Oki Electric Industry Co., Ltd. Research and Development, October 2000, No. 184, Vol. 67, No. 3, pp. 61 to 64).
In the conventional semiconductor device having the above-mentioned structure, since a side surface of the gate electrode
150
is not exposed when the contact holes
130
a
and
130
b
are to be formed, the sidewall insulating film
117
requires a certain thickness. Therefore, it is hard to reduce the thickness of the sidewall insulating film
117
. For this reason, when a space width between the word lines, that is, between the gate electrodes
150
is reduced, a contact area between the epitaxial layer
119
a
and the source/drain region
113
a
and that between the epitaxial layer
119
b
and the source/drain region
113
b
are decreased and an ele
Shiratake Shigeru
Takeuchi Masahiko
Nhu David
Renesas Technology Corp.
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