Decoding apparatus for semiconductor memory device, and...

Details Decoding apparatus for semiconductor memory device, and... Decoding apparatus for semiconductor memory device, and...

2002-12-30

2004-06-08

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S233500

Reexamination Certificate

active

06747909

ABSTRACT:

TECHNICAL FIELD
The present disclosure relates to a decoding apparatus for a semiconductor memory device, and more particularly, to an improved decoding apparatus configured to decode an address in the DRAM.
BACKGROUND
A semiconductor memory device includes an address latch and a decoder. One example of improving a driving operation between the address latch and the decoder has been disclosed in Japanese Patent Laid-Open 11-16362 ‘Memory data read circuit’ for controlling driving of an address decoding unit by using a built-in pulse generating circuit.
The address latch and the decoder are controlled to guarantee validity of addresses input to the decoder.
FIGS. 1 and 2
are block diagrams illustrating a conventional decoding apparatus for a semiconductor memory device.
Referring to
FIG. 1
, the conventional decoding apparatus includes an address latch
10
enabled according to an address latch control signal XAE for transmitting inputted addresses ADD<0-N> to a special bank, a delay unit
11
for delaying the address latch control signal XAE and generating a decoder control signal XAED, and a decoder
12
enabled according to the decoder control signal XAED for decoding latch addresses BXAZ<0-N> of the address latch
10
. As illustrated in
FIG. 2
, the decoder
12
can be divided into a predecoder
13
and a main decoder
14
.
Still referring to
FIG. 1
, when the address latch
10
receives an active command, it latches the inputted address ADD<0-N> in response to the address latch control signal XAE of the selected bank. Even if the inputted address ADD<0-N> is varied, the address latch
10
constantly maintains the output BXAZ<0-N> until it receives a precharge command.
As described above, the conventional decoding apparatus enables the decoder
12
by using the decoder control signal XAED obtained by delaying the address latch control signal XAE. That is, in order to guarantee validity of the addresses BXAZ<0-N> input to the decoder
12
(or predecoder
13
), the decoder control signal XAED is generated by delaying the address latch control signal XAE for a predetermined time.
However, the state of the output signal is varied due to variations of the process, temperature and voltage, and thus the address latch control signal XAE must be sufficiently delayed with a margin in order to generate the decoder control signal XAED. When the delay time is deficient, a glitch is generated in the output of the decoder
12
, thereby increasing current consumption or generating a mis-operation.
As a result, the conventional decoding apparatus for the semiconductor memory device generates signal transmission delay between the address latch and the decoder, and thus fails to improve an operation speed.
SUMMARY OF THE DISCLOSURE
A decoding apparatus configured to remove unnecessary delay between an address input to a decoder and a decoder control signal by enabling the decoder in response to the decoder control signal generated by logically combining an address latch control signal and an internal address according to an output signal from an address latch is disclosed herein.
The decoding apparatus for a semiconductor memory device includes: an address latch to output first and second latch addresses and an internal address by latching an input address in response to an address latch control signal; an address transition detector to generate a decoder control signal by logically operating the address latch control signal and the internal address according to the first and second latch addresses; and a decoder enabled according to the decoder control signal.
An enable method of a decoding apparatus for a semiconductor memory device includes the steps of: generating first and second latch addresses and an internal address by latching an input address in response to an address latch control signal; generating a decoder control signal by logically operating the address latch control signal and the internal address according to the first and second latch addresses; and enabling a decoder in response to the decoder control signal.


REFERENCES:
patent: 5438548 (1995-08-01), Houston
patent: 5694370 (1997-12-01), Yoon
patent: 5715208 (1998-02-01), Casper et al.
patent: 5764591 (1998-06-01), Matsui et al.
patent: 5831927 (1998-11-01), Casper et al.
patent: 5949737 (1999-09-01), Casper et al.
patent: 6385078 (2002-05-01), Jeon

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