Correction for pipelined analog to digital (A/D) converter

Details Correction for pipelined analog to digital (A/D) converter Correction for pipelined analog to digital (A/D) converter

2003-03-07

2004-08-31

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000

Reexamination Certificate

active

06784814

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to analog-to-digital (A/D) converters and conversion techniques. More particularly, the present invention pertains to correction of nonlinearity and gain error in A/D converters and conversion techniques, e.g., pipelined A/D converters.
FIG. 1
illustrates a conventional pipelined A/D converter
10
. The A/D converter
10
converts an analog electrical input signal Vin into a digital representation thereof Dout, e.g., analog samples of the input Vin are converted. Various illustrative exemplary n-bit A/D converters can be implemented. It should be understood that a resolution of any number of bits may be implemented uses a varied number of different stages
12
of the A/D converter
10
. In other words, the resolution of an A/D converter can be referred to as an n-bit A/D converter, where n represents the number of digital output bits. The A/D converter
10
has the analog input signal Vin provided on an initial stage
16
of the plurality of stages
12
. Each of the plurality of stages
12
of the A/D converter
10
converts a portion of the analog input Vin applied to input
14
, and as such contributes to the digital output representation Dout.
The pipelined A/D converter
10
receives the analog input Vin at the first stage
16
for processing. The first stage determines one or more bits. A residue R
0
representing the portion of the analog input Vin not converted by the initial stage
16
is generated and passed to a subsequent stage for processing to determine one or more digital bits. This process continues through each of the remaining stages
19
of the plurality of stages
12
which form part of the A/D converter
10
. In other words, when a prior stage completes processing of an analog input or a residue applied thereto, it provides for an analog residue to be applied to a next subsequent stage for analog to digital conversion and for application of an analog residue to the next subsequent stage. The prior stage is then ready to receive a new analog input sample or residue to process. In other words, a pipeline is filled.
Due to the time required to fill the pipeline, pipelining causes an initial latency in computing the digital representation corresponding to an analog input sample. However, pipelining increases the rate at which digital representations corresponding to sequential analog input samples are generated by the converter due to the parallel processing of the sampled analog input signal.
As shown in
FIG. 1
, the pipelined A/D converter
10
includes M pipelined stages
12
and a digital error correction (DEC) circuit (e.g., a combining circuit)
18
. The pipelined initial stage
16
receives the analog input signal Vin at input
14
. The pipelined stages
12
produce respective analog outputs, e.g., analog outputs
20
,
22
, or, in other words, analog residues such as R
0
from the first stage
16
. The analog residues (e.g., R
0
) from respective pipelined stages
12
are respectively coupled to the analog inputs of subsequent pipelined stages. For example, analog residue R
0
resulting from the initial stage
16
is coupled to stage
2
(one of blocks
19
of stages
12
).
Generally, each stage includes similar elements. For example, as shown in
FIG. 1
, stage
2
(one of blocks
19
of the stages
12
) includes a sample and hold circuit
30
, an analog-to-digital converter (ADC)
32
, a digital-to-analog converter (DAC)
34
, and a summing circuit
36
. The sample and hold circuit
30
receives the analog input signal
31
applied thereto (i.e., amplified analog residue R
0
) and holds the signal for later processing to generate the analog input of the next stage of the pipelined A/D converter
10
(i.e., stage
3
).
The ADC
32
performs an analog-to-digital conversion of the input signal resulting in N bits
35
to be provided to DEC circuit
18
. The N-bit digital output
35
of stage
2
is provided to DAC
34
for conversion to an analog signal
37
based thereon. The analog signal
37
is subtracted in summing circuit
36
from the held analog sample signal
39
to generate the analog residue
22
of stage
2
. In other words, the difference between the analog input to ADC
32
and the DAC
34
analog output provides the residue
22
. The residue
22
is amplified by an interstage amplifier
40
to provide an amplified residue
22
to be applied to stage
3
. In the exemplary embodiment of stage
2
, the amplification has a gain of 2
N
.
The digital outputs of each stage
12
(e.g., digital output
35
of stage
2
) are input to DEC circuit
18
. The DEC circuit
18
generates the digital output Dout of the A/D converter
10
, i.e., a series of bits, based on the digital outputs from all the stages
12
. For example, if the digital output includes D
M−1
to D
0
, and n=4 bits, then the digital output is D
3
, D
2
, D
1
, and D
0
, where D
3
is the most significant bit (MSB) and D
0
is the least significant bit (LSB). The DEC circuit
18
has, for example, a series of delays, or shift registers, to delay the digital output of each stage
12
so that the respective digital outputs for the same sampled signal can be combined.
Pipelined A/D converters are generally known and may be implemented in any number of ways. For further information regarding such conventional A/D converters, the following reference materials are provided: Stephen H. Lewis et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. Sc-22, no. 6, pages 954-961, Dec. 1987; Stephen H. Lewis et al., “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pages 351-358, March 1992; Thomas B. Cho et al., “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pages 166-172, March 1995; Krishnaswamy Nagaraj et al., “A 250-mW, 8-b, 52-Msample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pages 312-320, March 1997; and Yuh-Min Lin et al., “A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-&mgr;m CMOS,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pages 628-636, April 1991, each of which are incorporated by reference in their entireties.
As is apparent, the pipelined A/D converter
10
includes analog portions and digital portions. For example, the DEC circuit
18
is a digital component portion, whereas the DAC
34
, and interstage amplifier
40
, are analog portions. In practice, every analog component in the pipelined A/D converter
10
exhibit non-ideal circuit behavior that will tend to degrade the overall conversion performance of the converter
10
. For example, in typical switched capacitor implementations of DACs, noise or nonlinearity arises from the static capacitor mismatches employed in the digital-to-analog conversion performed thereby.
There is a speed/accuracy design tradeoff in the design of high-end pipelined A/D converters. Generally, the desired accuracy of a pipelined architecture is limited by nonlinearity, offset, and gain errors. For example, such errors may be introduced by the input sample and hold, the ADC of each stage, the DAC of each stage, and the interstage gain amplification of the analog residues provided by a stage to a subsequent stage. As indicated above, such various non-idealities in the A/D converter
10
result in errors, e.g., nonlinearity error, being present in the A/D converter transfer function and result in a corresponding reduction in performance of the A/D converter.
To meet the accuracy requirements as defined by the bits of A/D resolution, the nonlinearities must not exceed 1 least significant bit (LSB) in magnitude. Although the nonlinearities in a pipelined A/D converter may be less than 1 LSB, they may have a repetitive or periodic nature, which results in the generation of spurious tones in the frequency spectra of the digital representation of the analog input. An important measure of an A/D converter's performance is spurious free d

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