Overlay target design method to minimize impact of lens...

Details Overlay target design method to minimize impact of lens... Overlay target design method to minimize impact of lens...

2002-12-19

2004-06-29

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

C430S005000, C430S030000, C257S797000

Reexamination Certificate

active

06756167

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an overlay target design method for semiconductor fabrication to minimize the impact of lens aberrations on target projection.
DESCRIPTION OF RELATED ART
Typically semiconductor devices are fabricated by optical lithography techniques using a projection imaging systems. A typical projection image system
20
is illustrated in FIG.
1
. The system
20
at a minimum includes an illumination controller
22
and an illumination source
24
coupled with and controlled by controller
22
. Illumination source
24
may include, for example, a mirror, a lamp, a light filter, and a condenser lens system. As used herein, the term “light” refers to light used in photolithography. The term “light” need not be restricted to visible light, but may also include other forms of radiation and lithography. For example, energy supplied by lasers, photons, ion beams, electron beams, or X-rays are included within the term “light”.
Illumination source
24
emits light or radiation that can pass through openings in mask
26
. System
20
shows mask
26
positioned adjacent to light source
24
; optionally, other devices such as one or more optical lenses could separate light source
24
and mask
26
. The term “mask” is not limited to a physical structure, but also includes a digitized image used in, for example, electron beam and ion beam lithography systems. For example, mask
26
may include a pattern for projecting a wiring or feature pattern of an integrated circuit. The pattern of mask
26
may include various image structures, for example, clear areas, opaque areas, phase shifting areas, and overlay targets. Mask
26
generally is a combination of clear areas and opaque areas, where the clear areas allow light from light source
24
to pass through mask
26
to form the mask's image. Light passing through mask
26
is further transmitted by projection lens
30
, which may be, for example, a reduction lens or a combination of lenses for focusing the mask pattern onto a projection surface
111
, such as a semiconductor wafer covered with a photoresist layer. Typical semiconductor fabrication involves a four to ten times reduction of mask size
26
by projection lens
30
. Projection surface
111
is held in position by a holding device (not shown), which may be part of or controlled by a stepper (not shown). Also shown in
FIG. 1
is lens pupil
28
of projection imaging lens
30
, which defines the numerical aperture of lens
30
.
As the dimension of features on integrated circuits continue to decrease, the resolution limits of optical lithography are quickly being reached. One limit is caused by lens aberration, which is the failure of a lens, such as projection lens
30
, to produce exact point-to-point correspondence between a received image, such as from mask
26
, and a projection surface
111
, such as a semiconductor die
100
a portion of which is illustrated in FIG.
2
. One of the many types of lens aberrations in semiconductor device fabrication is coma aberrations which are optical aberrations that cause the image of a mask
26
to appear comet-shaped or blurred on die surface
113
(FIG.
2
). Coma aberrations result in not only line width variations and/or pattern asymmetry, but also affect the location or placement of the mask image on the die surface
113
. As discussed in Takashi Saito and Hisashi Watanabe's article “Investigation of New Overlay Measurement Marks for Optical Lithography,”
J. Vac Sci Technol. B
16(6), November/December 1998, pp. 3415, 3418, during sub-micron device fabrication using optical lithography lens aberrations cause different displacement errors for overlay targets and device patterns.
A target is a feature on a mask
26
, usually at the perimeter of the mask
26
, that is transferred to die surface
113
during the illumination phase. The target helps to determine if the image transfer from mask
26
to die surface
113
was properly aligned relative to lower layers. Typically, the quality of the lithographic image alignment is measured by determining the alignment of a target on a lower level to a target on an upper or overlay level. In general the image transfer is successful if the target of the upper-layer is approximately centered with the lower-level target. An, overlay measurement system is used to measure the distances and spaces between edges or boundaries of the upper and lower targets. It is critically important that the circuit pattern on one layer is accurately aligned with that of earlier layers. To evaluate the alignment of two layers, a target is formed on each layer.
FIG. 2
is an illustration of a single integrated circuit (IC) die
100
fabricated on a semiconductor wafer. The locations of the electrical circuit or pattern and targets are represented by large box
120
, hereinafter referred to as pattern, and small boxes
110
, hereinafter referred to as targets, respectively. Typical dimensions for die
100
are 5 millimeters by 5 millimeters and typical dimensions for targets
110
are 10 microns by 10 microns.
A prior art method of mask alignment measurement will be described with respect to
FIGS. 3 and 4
.
FIG. 3
is a top view of a prior art box-in-box target
110
of FIG.
2
.
FIG. 4
is a cross-sectional view of
FIG. 3
along line III—III. The accuracy of the transfer of the targets
110
approximates the accuracy of the pattern
120
transfer. A first target
112
with a box pattern can be formed on surface
113
in a first layer or under layer
115
using well known lithography techniques. Typically, a silicon oxide material is deposited over first layer
115
to form a second layer
116
. The second target
114
is formed in second layer
116
with dimensions smaller than target
112
using well known lithography techniques. The perimeter
117
of first target
112
and perimeter
118
of second target
114
can be viewed by optical measurement equipment. By measuring the distance between the two perimeters or isolated edges
117
,
118
at several locations, the center positions of targets
112
,
114
can be determined and positional deviations between the two targets
112
,
114
can be determined. The overlay measurement provides a comparison of the alignment of the underlay target
112
of layer
115
with that of overlay target
114
of layer
116
.
In the article by Saito and Watanabe the benefits of using fine pattern targets made up of thin lines instead of large box shaped patterns is discussed. Fine patterns targets, such as targets formed with thin line widths, are generally much closer to the actual circuit features dimensions than conventional large box patterns. Since lens aberrations typically induce line width variations and create alignment errors, using fine pattern targets allows more accurate detection of lens aberrations and alignment errors. In other words, the use of the typical box-in-box method (
FIGS. 3-4
) to determine mask
26
displacement errors is not very accurate for small device patterns, such as a quarter micron device fabrication (0.25 micron device feature size). Using targets with feature dimensions (size and pitch) similar to those of the circuit improves the detection of displacement errors.
For example,
FIG. 5
is an illustration of a conventional fine pattern target system
200
. Fine pattern targets
210
,
220
are formed in a first layer
215
(
FIG. 6
) over surface
213
. Fine pattern targets
230
,
240
are formed in a second layer
216
(
FIG. 6
) over first layer
215
.
FIG. 6
is a cross-sectional view of
FIG. 5
along line VI—VI. In known target systems such as target system
200
(FIG.
5
), the first layer targets
210
,
220
and second layer targets
230
,
240
generally have the same pitch (P1). The term “pitch” refers to the distance between the outside edge of a first target and the outside edge of a second target. For example in
FIGS. 5-6
, the pitch of targets
210
and
220
are the distance between the perimeter
211
of target
210
and the perimeter
212
of target
220
. In known tar

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