Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-13
2004-08-03
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185290
Reexamination Certificate
active
06771540
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a nonvolatile semiconductor storage device and a method for operating the nonvolatile semiconductor storage device, and more particularly to a nonvolatile semiconductor memory device enhanced for data retention characteristics, accuracy of program and erase operations.
BACKGROUND ART
For a nonvolatile semiconductor storage device in which each memory cell is composed of an FET transistor provided with a floating gate covered by an insulating film therearound and used as a charge storing layer, data is stored by controlling the amount of electrons stored in the floating gate thereby changing the threshold voltage of the transistor. When programming or erasing data into or from the memory cell, electrons are either injected or ejected from the floating gate via the insulating film.
Electron injection/ejection is possible by using the (Fowler-Nordheim (F-N)) tunnel phenomenon and the hot electron phenomenon. At this time, electrons are injected in the insulating film around the floating gate with the application of a high electrical field. Consequently, when the number of program/erase cycles is increased, the insulating film receives an electron injection stress repetitively, thereby degrading the insulating film. This results in the degradation of the various properties of the memory cell. Especially, when a low electrical field is applied to the insulating film that has been degraded due to such repetitive program/erase operations, the leakage current (low electric field leakage current or stress-induced leakage current) is increased. Consequently, the electron retention characteristics or the disturb characteristics of the memory cell are degraded. This degradation has now been questioned as a factor to limit the program/erase cycles for such a nonvolatile semiconductor memory device.
For example, Mr. Endoh and others disclosed a method, as described in the first related art example, for improving the read disturb characteristics of memory cells by suppressing the above mentioned stress-induced leakage current in the 1994 International Electron Devices Meeting 3.3, and in the 1995 Springtime Applied Physics Academy Scientific Lecture Meeting (30p-R-6). Hereunder, the outline of this method will be described with reference to FIG.
4
.
FIG.
4
(
a
) is a timing flow of voltages applied to a memory cell in an erase operation. FIG.
4
(
b
) is a cross sectional view of a memory cell. In the first related art example, data is programmed/erased in a memory cell by injecting/ejecting electrons in/from the floating gate
42
via the gate insulating film
46
rising the F-N tunnel phenomenon. In this example, ejection of electrons from the floating gate
42
is defined as an erase operation. If this erase operation is repeated many times using the F-N tunnel phenomenon, the gate insulating film
46
of each memory cell is degraded as described above, and as a result, the stress-induced leakage current is increased. In this first related art example, it is considered that an increase of the stress-induced leakage current occurs via many trap sites formed in the insulating film along with the progress of the degradation of the gate insulating film.
Therefore, in order to prevent this stress-induced leakage current in the first related art example, an erase operation is performed as to be described later, in order to deactivate trap sites as follows.
At first, the control gate is set to the ground potential and a predetermined positive erase voltage Vee is applied to the substrate
45
, the source
43
, and the drain
44
of an object memory cell. Then, electrons are ejected from the floating gate toward the substrate
45
via the gate insulating film
46
using the F-N tunnel phenomenon, thereby setting the threshold voltage of the memory cell to a predetermined erase level. At this time, trap sites in the gate insulating film
46
are activated by the applied high voltage Vee.
Immediately following this erase operation, a positive voltage Vgg is applied to the control gate
41
for a sufficient amount of time to deactivate the trap sites. The voltage Vgg must be a voltage that can suppress a program operation, that is, a low voltage that can suppress the variation of the threshold voltage from a predetermined erase level. The voltage Vgg must also have the same polarity as that of the read operation, and have a larger voltage than the voltage in the read operation.
With this application of the positive low voltage Vgg, the number of trap sites active in the read operation is reduced at the phase boundary between the gate insulating film
46
and the substrate
45
, as well as near the phase boundary. And accordingly, the stress-induced leakage current is reduced, thereby making it possible to suppress the variation of the threshold voltage caused by a read operation and improve the read retention characteristics after that.
In a memory cell whose gate insulating film is degraded due to repetitive program/erase operations, however, a variation of the threshold voltage also occurs due to a leakage of many electrons trapped in the gate insulating film in addition to an increase of the stress-induced leakage current. Mr. Kato and others made this clear (referred to in the 1994 International Electron Devices Meeting 3.2).
It is well known that many charged trapping centers are formed in the gate insulating film depending on the program/erase operation method if the program/erase operation is repeated. When electrons pass through the insulating film during program/erase operation, some of the electrons are trapped by those charged trapping centers. Those trapped electrons leak more easily out of the insulating film than the electrons stored in the floating gate. The threshold voltage of the memory cell is thus varied sharply and quickly after a program/erase operation, thereby affecting the data retention characteristics significantly. Therefore, in order to improve the data retention characteristics of the memory cell, it is very important to reduce both the trapped electrons in the insulating film
46
and the stress-induced leakage current.
FIG. 13
shows the distribution of electrons trapped in the gate insulating film
46
during an erase operation of the first conventional technology. FIG.
13
(
a
) is an explanatory view of the electron distribution when an erase voltage Vee is applied toward the substrate
45
, and FIG.
13
(
b
) shows an explanatory view of the electron distribution when a positive-low voltage Vgg is applied toward the control gate
41
after the application of the erase voltage. As shown in FIG.
13
(
a
), when the erase voltage Vee is applied, some of the electrons ejected from the floating gate
42
to the gate insulating film
46
are trapped by the charged trapping centers existing near the floating gate
42
in the gate insulating film
46
. In addition, electron ejection occurs near the phase boundary of the substrate in the gate insulating film
46
occurs electron ejection.
Consequently, the distribution of trapped electrons becomes as follows; too many electrons gather at the floating gate
46
side and fewer electrons gather at the substrate
45
side (or holes are excessive). If the application of the erase voltage Vee is finished in such a distribution state, too many electrons or holes are distributed in the gate insulating film
46
, and as a result the inner electric field becomes a dominant force. Electrons or holes are then ejected from the gate insulating film
46
to ease this dominant force. This phenomenon, however, invites a variation of the threshold voltage, which will reduce the margin between the threshold voltage and the program level of a memory cell from which data is erased. As a result, the data retention characteristics of the memory cell is degraded.
In the first related art example, trap sites are deactivated with a positive low voltage Vgg, which is applied after the application of an erase voltage Vee to suppress the stress-induced leakage current. The voltage Vgg is a little hig
Kawahara Takayuki
Satoh Akihiko
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Phan Trong
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