Static information storage and retrieval – Read only systems
Reexamination Certificate
2003-04-22
2004-11-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read only systems
Reexamination Certificate
active
06822889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a nonvolatile memory (NVM). In particular, the present invention relates to a multi-level read only memory (ROM) and method for producing the same.
2. Description of the Related Art
Mask ROM is generally made from a number of cell transistors, each serving as a memory unit. When programming is required, ions are implanted into the channel region of selected memory cells so that threshold voltage of these cells is modified, this step also being referred to as code implantation. The “on” or “off” state of each memory cell is thus set. The memory cell is formed in the word line (WL) covered area between two neighboring bit lines (BL). Each memory cell is capable of storing a binary bit of data, either in a logic state of “0” or “1” depending on whether the channel region of the memory cell is implanted or not.
However, when the generation of the mask ROM fabrication is migrated into deep-sub-micro semiconductor process, higher integration of the integrated circuit corresponds with smaller size of the semiconductor device. When ions are implanted into the channel region of selected memory cells, the implanting region may suffer from misalignment, shifting the threshold voltage of transistors. If the implanting region is misaligned, it may be shifted in the direction of word line or bit line, directly causing data storage error of the ROM cell and disturbing the neighboring implanting regions to affect operating properties of the memory cell, especially in the shift of word line direction.
In addition, in a high density MASK ROM (such as 32M, 64M or higher), the conventional two state MASK ROM takes up a large wafer area because of the larger chip size.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a multi-level ROM coded by Vt implantation and oxidation.
Another object of the present invention is to provide a method for forming a multi-level ROM coded by Vt implantation and oxidation.
Still another object of the present invention is to provide a ROM layout which can be coded by contact via.
Still another object of the present invention is to provide a multi-level ROM layout which can be coded by contact via, Vt implantation and oxidation.
Still another object of the present invention is to provide an embedded ROM.
The present invention provides a multi-level ROM coded by Vt implantation and oxidation. Each ROM cell has four selections of ROM code. The first ROM code with threshold voltage Vt
1
is performed with one Vt implantation and has a thin gate oxide layer. The second ROM code with threshold voltage Vt
2
is performed with two Vt implantations and has a thin gate oxide layer. The third ROM code with threshold voltage Vt
3
is performed with one Vt implantation and has a thick gate oxide layer. The fourth ROM code with threshold voltage Vt
4
is performed with two Vt implantations and has a thick gate oxide layer.
The present invention provides a multi-level ROM with two thicknesses of gate oxide layer and two Vt adjusting recipes available for each ROM cell. Thus each ROM cell has four ROM codes for selection. The first ROM code is performed with first Vt adjusting recipe and has a thin gate oxide layer. The second ROM code is performed with second Vt adjusting recipe and has a thin gate oxide layer. The third ROM code is performed with first Vt adjusting recipe and has a thick gate oxide layer. The fourth ROM code is performed with second Vt adjusting recipe and has a thick gate oxide layer.
The present invention provides a method for forming a multi-level ROM, with two thicknesses of gate oxide layer and two Vt adjusting recipes are chosen for each ROM cell. After defining the active device region, well processes are performed. When forming well regions in the cell region, Vt adjusting recipes are also performed. The first Vt adjusting recipe is such as performing one Vt implantation, and the second Vt adjusting recipe is such as performing two Vt implantations. Then, two different thickness of gate oxide are performed. Thereby, the ROM cells are coded.
The present invention provides another programming method, in which the ROM cell is programmed by connecting or disconnecting to bit line through contact window. After forming transistors of a contact-ROM layout circuit, contact windows are formed in an insulating layer covering the transistors. Bit lines are formed on the insulating layer and the contact windows, and each transistor can connect or disconnect to bit line through the contact windows.
Furthermore, the first programming method of adjusting threshold voltage and the second programming method of connecting or disconnecting to bit line through contact window are combined, and each ROM cell has five ROM codes for selection. The first ROM code forms the first transistor with threshold voltage Vt
1
by performing the first Vt adjusting recipe and forming thin gate oxide layer. The second ROM code forms the second transistor with threshold voltage Vt
2
by performing second Vt adjusting recipe and forming thin gate oxide layer. The third ROM code forms the third transistor with threshold voltage Vt
3
by performing the first Vt adjusting recipe and forming thick gate oxide layer. The fourth ROM code forms the fourth transistor with threshold voltage Vt
4
by performing second Vt adjusting recipe and forming thick gate oxide layer. The fifth ROM code disconnects the transistor to bit line.
The method for forming the ROM with five ROM codes is simply described herein. After defining active device region, well processes are performed. When forming well regions in the cell region, Vt adjusting recipes are also performed. The first Vt adjusting recipe is such as performing one Vt implantation, and the second Vt adjusting recipe is such as performing two Vt implantations. Then, two different thickness of gate oxide are performed. These transistors then connect or disconnect to bit line through contact window, and the ROM cells are coded.
REFERENCES:
patent: 6577536 (2003-06-01), Chung et al.
Chen Ying-Tzuo
Hwang Jung-Ren
Elms Richard
Luu Pho M.
Macronix International Co. Ltd.
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