Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2000-08-08
2004-06-29
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S214000, C700S103000
Reexamination Certificate
active
06757577
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for managing work-in-process (WIP) workload within fabrication facilities. More particularly, the present invention relates to methods for efficiently managing work-in-process (WIP) workload within fabrication facilities.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, so also has increased the complexity of microelectronic fabrication processing methods and microelectronic fabrication facilities that are employed for fabricating microelectronic fabrications. The increased complexity of microelectronic fabrication processing methods and microelectronic fabrication facilities derives in-part from the length (i.e., total number of process steps) of a typical microelectronic fabrication process description, along with the variety of microelectronic fabrication process tools that is typically employed for fabricating a typical microelectronic fabrication, further in conjunction with the variety of individual microelectronic fabrications (i.e., part numbers) that is typically fabricated within a typical microelectronic fabrication facility.
Further contributing to the complexity of microelectronic fabrication processing methods and microelectronic fabrication facilities is the generally distributed nature of microelectronic fabrication processing methods and microelectronic fabrication facilities, which further allows for various production priorities and dispatching rules when fabricating multiple microelectronic fabrication part numbers within either individual or multiple microelectronic fabrication facilities. Such varied production priorities and dispatching rules in-turn often provide difficulties in management of microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
In light of the foregoing, it is thus desirable in the art of microelectronic fabrication to provide systems and methods for efficiently managing microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
Various systems and methods have been disclosed in the arts of manufacturing and fabrication for managing fabrication workload within fabrication facilities, such as but not limited to microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
For example, Weng, in U.S. Pat. No. 5,612,886, discloses a system and a method for managing, with enhanced efficiency, semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload within a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method employ a dynamic dispatching algorithm that in turn employs a sorting of semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload by both priority and queue time, and further wherein the dynamic dispatching algorithm incorporates both semiconductor substrate release rules and semiconductor integrated circuit microelectronic fabrication dispatch rules.
In addition, Pan et al., in U.S. Pat. No. 5,748,478, disclose a system and a method for optimizing output workload of a fabrication facility, such as but not limited to a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method provide, in general, for determining a work-in-process (WIP) workload inflow within the fabrication facility, for determining a work-in-process (WIP) workload output within the fabrication facility and for calculating a work-in-process (WIP) workload flow intensity within the fabrication facility.
Further, Chin. et al., in U.S. Pat. No. 5,818,716, also disclose a system and a method for managing, with enhanced efficiency. work-in-process (WIP) workload within a fabrication facility, such as but not limited to semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload within a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method employ a required turn rate (RTR) algorithm that determines not only a due date and a production priority for the work-in-process (WIP) workload within the fabrication facility, but also provides for local dispatching of the work-in-process (WIP) workload within the fabrication facility.
Finally, Dangat et al., in U.S. Pat. No. 5,971,585, discloses a method for optimizing within a fabrication facility, such as but not limited to a microelectronic fabrication facility, fabrication assets with respect to fabrication demands, such as to determine which fabrication demands may be met, and thus manage a workload within the fabrication facility. To realize the foregoing object, the method employs a best can do (BCD) algorithm for matching the fabrication assets with respect to fabrication demands, where the best can do (BCD) algorithm comprises a forward implode feasible plan solver which may alternatively employ either heuristic decision technology or linear programming decision technology.
Desirable in the art of microelectronic fabrication are additional systems and methods that may be employed for managing microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a system and a method for managing microelectronic fabrication work-in-process (WIP) workload within a microelectronic fabrication facility.
A second object of the present invention is to provide a system and a method in accord with the first object of the present invention, which system and method are readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a system and a method for managing within a fabrication facility, such as but not limited to a microelectronic fabrication facility, a work-in-process (WIP) workload, such as but not limited to a microelectronic fabrication work-in-process (WIP) workload.
To practice the method of the present invention, there is first provided a fabrication facility comprising: (1) a minimum of one pre-process tool, which in turn provides an available work-in-process (WIP) pre-process rate; (2) a minimum of one buffer tool, which in turn provides an available work-in-process (WIP) buffer capacity; and (3) a minimum of one post-process tool, which in turn provides an available work-in-process (WIP) post-process rate, wherein a work-in-process (WIP) workload within the fabrication facility is sequentially pre-processed within the minimum of one pre-process tool, buffered as needed within the minimum of one buffer tool pending availability of the minimum of one post-process tool, and then post processed within the minimum of one post-process tool. There is then determined for the fabrication facility a buffer tool tolerance time predicated upon the available work-in-process (WIP) pre-process rate, the available work-in-process (WIP) buffer capacity and the available work-in-process (WIP) post process rate, beyond which buffer tool tolerance time the available work-in-process (WIP) buffer capacity is exceeded when operating the fabrication facility. In addition, there is then halted, when operating the fabrication facility, operation of the minimum of one pre-process tool prior to exceeding the buffer tool tolerance time.
The method of the present invention contemplates a system, and in particular a co
Cheng Po-Win
Jeng Bo-Chan
Mao Wei-Shan
Garland Steven R.
Picard Leo
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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