Synchronizer with zero metastability

Details Synchronizer with zero metastability Synchronizer with zero metastability

2003-02-12

2004-08-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S145000

Reexamination Certificate

active

06771099

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to digital logic, and, more particularly, to digital logic devices that receive asynchronous inputs.
BACKGROUND OF THE INVENTION
In the world of computer technology, a system may include an interface to an external system. For example, a processor-based system may interface to a variety of external systems, including keyboards, modems, printers, interrupts, and other input/output (I/O) devices. These extemal systems may be essential to the functionality of the underlying system.
The external systems are frequently asynchronous to the underlying system. In other words, the extemal system is typically not bed to the internal clock mechanism of the underlying system, but, instead, operates independently and asynchronously to the underlying system.
Asynchronous inputs may be problematic for the most basic elements of the system, including digital logic components. For example, an asynchronous input to a flip-flop that violates the setup and hold times of the device may cause thee flip-flop to become unpredictable, or metastable.
In fact, such metastable behavior is expected. Specifications for flip,-flops, for example, include statistical parameters, which allow system designers to calculate information such as Mean Time Between Failures, or MTBF. The MTBF of a device indicates the likelihood of a metastable condition occurring in the device.
To avoid the metastable condition, the signal being received by the circuit, or input signal, is expected to not change and to maintain a proper logic level while being sampled by the clock. T
SU
, or setup time, is the time just prior to a clock transition. The input signal is expected to remain stable for a time period of T
SU
or greater prior to the clock transition. T
H
, the hold time, is the time just after the clock transition. The input signal is expected to remain stable for a time period of T
H
or greater after the clock transition. Changes to the input signal that occur between T
SU
and T
H
may produce unpredictable results.
Asynchronous inputs may produce metastability. Since an asynchronous input can change at any time relative to the clock, the input may be change between T
SU
and T
H
. Various design techniques may reduce the probability of a metastable event occurring, but do not eliminate metastability.
Logic designers include circuitry, such as synchronizers, to minimize the possibility of a metastable output from a circuit. The MTBF caused by metastability is inversely proportional to the clock and data frequency. As the clock frequency increases, the time between failures decreases, such that the number of failures increases when the clock frequency increases. With lower clock frequencies, however, a lower sampling resolution, and thus, higher jitter in the synchronized data stream, is produced. Digital logic designers thus tradeoff the amount of jitter that is introduced into the synchronized signal and an acceptable MTBF.
As system clock frequencies increase, the metastability problem likewise increases. In some environments, metastability adversely affects system reliability. Where unexplained system crashes and other unresolved failures occur, metastability may be the culprit.
There exists a widely held belief that metastability cannot be eliminated entirely and that a synchronizer cannot completely eliminate metastability when sampling an asynchronous signal.
SUMMARY OF THE INVENTION
In one embodiment, a system is disclosed comprising a first flip-flop with an input tied to a constant logic level, an asynchronous input, a clock input, and an output, a second flip-flop coupled as a toggler, the second flip-flop comprising a clock input coupled to the output of the first flip-flop and an output. An asynchronous signal is received into the asynchronous input of the first flip-flop and a synchronized signal is received from the output of the second flip-flop.
In a second embodiment, a method is disclosed in which a first constant logic level signal is received by a first flip-flop input an asynchronous signal is received by a first flip-flop asynchronous input, a first flip-flop output signal is received by a second flip-flop clock input, and a first synchronized signal is produced in which the first synchronized signal is synchronized to a system clock received by a first flip-flop clock input.
Advantages and other features of the invention will become apparent from the following description, the drawings, and the claims. dr
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a block diagram of the synchronizer according to one embodiment of the invention;
FIG. 2
is a block diagram of the core of the synchronizer of
FIG. 1
according to one embodiment of the invention;
FIG. 2A
is a block diagram of the core of the synchronizer of
FIG. 1
with a combiner according to one embodiment of the invention;
FIG. 3
is a timing diagram of the core of
FIG. 2
according to one embodiment of the invention;
FIG. 4
is a block diagram of the combiner circuit of
FIG. 1
according to one embodiment of the invention;
FIG. 4
a
is a block diagram of the combiner circuit of
FIG. 1
according to a second embodiment of the invention;
FIGS. 5A-5C
are block diagrams of circuits equivalent to the core of
FIG. 2
according to one embodiment of the invention;
FIG. 6
is a block diagram of the core and the asynchronous recovery circuit of
FIG. 1
according to one embodiment of the invention;
FIG. 7
is a block diagram of the asynchronous recovery circuit and the pulse width discriminator of
FIG. 1
according to one embodiment of the invention;
FIGS. 8A-8D
are timing diagrams of the pulse width discriminator of
FIG. 7
according to one embodiment of the invention;
FIG. 9
is a block diagram of the inversion corrector of
FIG. 1
according to one embodiment of the invention;
FIG. 10
is a first variant of the synchronizer of
FIG. 1
according to one embodiment of the invention;
FIG. 11
is a second variant of the synchronizer of
FIG. 1
according to one embodiment of the invention;
FIG. 12
is a timing diagram of the synchronizers of
FIGS. 10 and 11
according to one embodiment of the invention; and
FIG. 13
is a block diagram of a synchronizer with a stage one voter according to one embodiment of the invention.


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