Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-08-30
2004-08-31
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S077000, C326S063000, C326S080000
Reexamination Certificate
active
06784718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the invention relates to a configuration of an input circuit adaptable to multiple types of interfaces. More specifically, the invention relates to a configuration of an input circuit of a synchronous semiconductor device operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 18
schematically shows an exemplary configuration of a conventional input circuit. Referring to
FIG. 18
, input circuit
902
includes a comparison circuit
902
a
for comparing an externally supplied signal EXSI with a reference voltage VREF to generate a signal according to a result of comparison, and an inverter
902
b
buffering (amplifying) the output signal from comparison circuit
902
a
to generate internal signal INSI. Comparison circuit
902
a
and inverter
902
b
receive internal power supply voltage VDDP as an operating power supply voltage.
Reference voltage VREF is generated by a reference voltage generation circuit
900
. Reference voltage generation circuit
900
includes a constant current source
900
a
, connected to an external power supply node which receives external power supply voltage EXVDD, for generating a constant current of a constant magnitude, and a current/voltage converting element (Z)
900
b
converting the constant current supplied from constant current source
900
a
into a voltage to generate reference voltage VREF on a node
900
c
. Current/voltage converting element
900
b
is constituted of a resistance element or a MOS transistor (insulated gate field effect transistor) having a gate and a drain connected together, for example.
FIG. 19
is a signal waveform diagram representing an operation of the input circuit shown in FIG.
18
. The operation of the input circuit shown in
FIG. 18
is now described briefly with reference to FIG.
19
.
Comparison circuit
902
a
has a negative input receiving external signal EXSI and a positive input receiving reference voltage VREF to function as a differential amplifier circuit.
When external signal EXSI is higher than reference voltage VREF, the output signal from comparison circuit
902
a
is at a low level according to the difference in between. Inverter
902
b
amplifies and inverts the low level signal from comparison circuit
902
a
to output the resultant signal, and thus internal signal INSI attains a logical high level (hereinafter H level) at the level of internal power supply voltage VDDP.
When external signal EXSI is lower than reference voltage VREF, comparison circuit
902
a
outputs a high level signal according to the difference in between. Inverter
902
b
inverts and amplifies the output signal from comparison circuit
902
a
, and thus internal signal INSI attains a logical low level (hereinafter L level) at the ground voltage level.
In this way, internal signal INSI has its logic level quickly changeable each time external signal EXSI crosses reference voltage VREF. Thus, the internal signal having a waveform with sharp rising/falling can be generated. In other words, with this differential amplifier circuit
902
a
, external signal EXSI is compared with reference voltage VREF to generate internal signal INSI according to a result of comparison, so that an internal signal having a sharp rising/falling can be generated even if external signal EXSI is distorted in waveform.
Reference voltage VREF is set to a voltage level according to the amplitude of the external signal, or the intermediate level of the amplitude of external signal EXSI. For example, if external signal EXSI is 1.8 V (=VDDQ), reference voltage VREF is set at 0.9 V.
FIG. 20
schematically shows a relation between the logical high level (H level) and the logical low level (L level) of external signal EXSI and the reference voltage. Referring to
FIG. 20
, the lower limit of H level of external signal EXSI is the level of voltage VIH while the upper limit of L level thereof is the level of voltage VIL. In general, for an LVTTL (Low Voltage Transistor Transistor Logic) interface, the lower limit voltage of H level, VIH, is set at 2.0 V, and the upper limit voltage of L level, VIL, is set at 0.8 V. Accordingly, for this LVTTL interface, reference voltage VREF is set at the intermediate value in between, i.e., 1.4 V.
However, for a recent 1.8 V interface used for transferring signal/data by means of an output circuit of a low power supply voltage, the H level lower limit voltage VIH is set at the voltage level of 0.8·VDDQ and the L level upper limit voltage VIL is set at the voltage level of 0.2·VDDQ, where VDDQ represents an operating power supply voltage of a circuit driving the external signal EXSI. In this case, reference voltage VREF has its voltage level set at the intermediate value, i.e., 0.9 V.
Referring back to
FIG. 18
, reference voltage VREF is generated through conversion of the constant current from constant current source
900
a
into voltage by current/voltage converting element
900
b
. Reference voltage VREF thus has a constant voltage level which is independent of voltage VDDQ. Power supply voltage VDDQ is allowed to vary within the range from 1.65 V to 1.95 V in the specification value.
Referring to
FIG. 21A
, when power supply voltage VDDQ increases to 1.95 V, H level lower limit voltage VIH of external signal EXSI attains 1.56 V while L level upper limit voltage VIL thereof attains 0.36 V. Reference voltage VREF is constant at 0.9 V, so that the difference between reference voltage VREF and H level lower limit voltage VIH is 0.66 V while the difference between reference voltage VREF and L level upper limit voltage VIL is 0.54 V. Accordingly, there is a difference between the time required for external signal EXSI of H level to change toward L level to cross reference voltage VREF and the time required for external signal EXSI of L level to change toward H level to cross reference voltage VREF. Consequently, the response of the internal signal to the falling of the external signal is delayed.
Referring to
FIG. 21B
, when power supply voltage VDDQ decreases to 1.65 V, H level lower limit voltage VIH attains 1.32 V while L level upper limit voltage VIL transitions to 0.32 V. Reference voltage VREF is also 0.9 V, and thus the difference between H level lower limit voltage VIH and reference voltage VREF is 0.42 V while the difference between reference voltage VREF and L level upper limit voltage VIL is 0.58 V. Consequently, the response of the internal signal to rising of the external signal is delayed.
Specifically, as shown with some exaggeration in
FIG. 22A
, when power supply voltage VDDQ increases, the response of internal signal INSI to the falling of external signal EXSI is delayed and the response thereof to the rising of external signal EXSI is advanced. Thus, the period during which internal signal INSI is at H level is shorter than that of an ideal response waveform indicated by the dotted line in FIG.
22
A.
In contrast, as shown in
FIG. 22B
, when the power supply voltage VDDQ decreases, the level of reference voltage VREF relatively increases. Then, the response of internal signal INSI to the falling of external signal EXSI is advanced while the response thereof to the rising of external signal EXSI is delayed. Consequently, the period of H level of internal signal INSI is longer than that of an ideal response waveform indicated by the dotted line in FIG.
22
B.
In other words, the variation in the level of power supply voltage VDDQ which defines H level of external signal EXSI causes delay in the rising or falling response of internal signal INSI, resulting in a problem that an internal signal responding accurately to change of an external signal cannot be generated.
It is considered that external signal EXSI changes between H level lower limit voltage VIH and L level upper limit voltage VIL due to a propagation loss of a signal transmission line. Then, the difference between H level lower limit voltage VIH and reference voltage VREF would become
Jinbo Shinichi
Matsumoto Junko
Okamoto Takeo
Suwa Makoto
Yamauchi Tadaaki
Nguyen Minh
Renesas Technology Corp.
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