Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2004-03-25
2004-11-09
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185280, C365S185270, C365S063000, C365S061000, C365S175000
Reexamination Certificate
active
06816410
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to low cost, high-density semiconductor memories and, in particular, to one-time-programmable semiconductor memories. More particularly, the invention relates to the field of vertically stacked field programmable non-volatile memory, support circuits useful therewith, and methods of fabrication thereof.
Recently there has been an interest in fabricating memories having memory cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction which are vertically separated from a plurality of parallel spaced-apart second lines in a second direction, for example, extending perpendicular to the first lines. Cells are disposed between the first lines and second lines at the intersections of these lines. These memories are described, for example, in U.S. Pat. Nos. 5,835,396 and 6,034,882.
Another way of fabricating three-dimensional memory arrays departs from the structures shown in these patents and uses “rail-stacks” as described in U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000, which application describes a memory employing antifuses where a diode is formed upon programming a particular bit. In this connection see, “
A Novel High
-
Density Low
-
Cost Diode Programmable Read Only Memory
,” by de Graaf, Woerlee, AHart, Lifka, de Vreede, Janssen, Sluijs and Paulzen, IEDM-96, beginning at page 189 and U.S. Pat. Nos. 4,876,220; 4,881,114 and 4,543,594.
SUMMARY OF THE INVENTION
A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The plurality of X-lines on a given layer is associated with both a memory plane above the layer and another memory plane below the layer. Likewise, the plurality of Y-lines on a given layer is associated with both a memory plane above the layer and another memory plane below the layer. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack.
In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. In particular, in a write mode high-voltage drivers for the row lines and column lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell.
By arranging the memory array with memory cells in all memory planes oriented in the same direction, a preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N
2
memory cells, rather than 3N
2
memory cells as with back-to-back diode stack memory arrays.
REFERENCES:
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6291836 (2001-09-01), Kramer et al.
Kleveland Bendik
Scheuerlein Roy E.
Matrix Semiconductor Inc.
Yoha Connie C.
Zagorin O'Brien & Graham LLP
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