Nonvolatile semiconductor memory device and data readout...

Details Nonvolatile semiconductor memory device and data readout... Nonvolatile semiconductor memory device and data readout...

2003-02-14

2004-11-23

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250, C365S205000, C365S210130

Reexamination Certificate

active

06822907

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile semiconductor device memory devices and data readout methods for the same, and more particularly to techniques used in flash memories or the like provided with a differential-type sense amplifier circuit.
Recently, dynamic sensing employed in DRAMs, for example, has been proposed for nonvolatile semiconductor memory devices requiring high-speed operability. Dynamic sensing is a method for reading data by directly comparing and amplifying the information of a memory cell connected to a bit line and the information of a reference cell connected to a reference bit line using a sense amplifier circuit. Dynamic sensing allows anti-noise characteristics to be increased through the combination of a folded bit line architecture and a differential sense amplifier circuit, and is considered particularly useful for circuits requiring high-speed operability. Also, not only does dynamic sensing allow high-speed operability, but a high-sensitivity data readout operation can also be anticipated because dynamic sensing can be used to directly determine the state of a memory cell.
However, with dynamic sensing in which a differential sense amplifier circuit is used, an examination of the conventional technology has shown that when the activation timing of the sense amplifier circuit is delayed in order to increase the accuracy of the determination level when data are read from the memory cell, the charge of the bit line set to the precharge potential is discharged by the cell current of the memory cell and the cell current of the reference cell, and this makes accurate data readout difficult. This problem is examined below with reference to FIG.
8
.
FIG. 8
shows the change in the potential of the bit line and the reference bit line when data are read by dynamic sensing using a conventional nonvolatile semiconductor memory device. In a preferable design, at the sense activation timing SENSE TIMING@Read of an ordinary readout operation, the reference potential Reference that is generated by the reference cell is a potential precisely in the middle between the potential Memcell@Prog on the write side of the memory cell and the potential Memcell@Erase on the erase side of the memory cell. However, if dynamic sensing is used in a verification operation for determining whether the memory cells of nonvolatile semiconductor memory devices, namely flash EEPROMs or the like, have been erased or written to a desired state, then when the activation timing of the sense amplifier circuit is slowed down to the readout timing SENSE TIMING@Verify for verification in order to increase the determination accuracy, the potential of the bit line is significantly lowered by the cell current of the memory cell and the cell current of the reference cell and flattens out, and thus readout determination at the desired timing is precluded.
To keep the bit line voltage from flattening out at the time of the readout operation, in the prior art a proposal has been set forth in JP H11-191298A for a method with which, as schematically shown in
FIG. 9A
, the potential of the reference bit line MBL
0
is held constant at the precharge potential, and a ½ current supply circuit d is provided for supplying a current of roughly half the value of the current flowing to the memory cell c to the bit line MBL
1
, to which data from the memory cell c have been read, in a direction that cancels out the current of the memory cell c, either during and after precharging or only after precharging.
However, with this conventional configuration, when the ½ current supply circuit d is affected by noise such as fluctuations in the power source, the amount of current that it supplies to the bit line MBL
1
is changed, leading to a reduction in the operation margin at the desired activation timing of the sense amplifier circuit SAMP. To compensate for the operation margin it becomes necessary to delay the activation timing of the sense amplifier circuit SAMP, and as a result the high-speed data readout operation is compromised.
FIG. 9B
shows the potential change in the bit line MBL
1
and the reference bit line MBL
0
during conventional data readout. Even if the power source voltage VSA of the ½ current supply circuit d of
FIG. 9A
is a stabilized power source that is not dependant on an outside voltage and is generated within the device, if a control signal HPC
0
for controlling the gate voltage of the p-channel transistor making up the ½ current supply circuit d is affected by power source fluctuations or coupling noise between adjacent signal wires during the data readout operation and thereby fluctuated, then the current supplied from the ½ current supply circuit d is changed at this time. For example, when an actually supplied supply current Ia is small enough that Ia<½×Imem, where ½×Imem is approximately half the value of the current Imem that is actually supplied to the memory cell c, then as shown by the short dashed lines and the long-short dashed lines in
FIG. 9B
, the difference in potential with respect to the reference voltage Reference is increased at the erase potential Memcell@Erase of the memory cell c, whereas the potential difference is reduced at the write potential Memcell@Prog of the memory cell c. On the other hand, when the supplied current is large enough that Ia>½×Imem, then the converse is true, and at the erase potential Memcell@Erase of the memory cell c there is a small potential difference with respect to the reference voltage Reference whereas at the write potential Memcell@Prog of the memory cell c there is a large potential difference. For this reason, the characteristics of the potential change at the memory cell c are unstable even if the reference potential is held constant and stabilized at the precharge potential, and thus extra time is required before a desired potential difference that is readable by the differential sense amplifier circuit SAMP is reached, which hinders high-speed readout. Also, when the amount of supplied current fluctuates during the verification operation, in which an infinitesimal current difference is determined by the differential sense amplifier circuit SAMP, or during measurement of the current of the memory cell c, for example, the amount of current that cancels out the cell current of the memory cell c itself is varied, and thus accurate results are difficult to obtain.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a nonvolatile semiconductor memory device and a data readout method for the same, with which an accurate and high-speed data readout operation and a high-precision data readout operation are possible.
To achieve the above object, the configuration of the present invention allows an identical amount of current to be supplied to bit line to which memory cell is connected and to bit line to which reference cell is connected when data is read from memory cell.
More specifically, a nonvolatile semiconductor memory device of the invention is characterized in that it is provided with a word line connected to a control gate of a memory cell in a row direction, a first bit line connected to a drain side of a memory cell in a column direction, a reference word line connected to a gate of a reference cell in the row direction, a second bit line connected to a drain side of a reference cell, an amplifier for amplifying a potential difference between the first bit line and the second bit line, a precharge circuit for precharging the first and the second bit lines to a predetermined potential at the start of data readout, and a bit line current supply circuit for supplying a same current amount to the first and the second bit lines during the data readout.
Another nonvolatile semiconductor memory device of the invention is characterized in that it is provided with a memory array including a plurality of memory cells and reference cells, a plurali

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