Gate voltage reduction in a memory read

Details Gate voltage reduction in a memory read Gate voltage reduction in a memory read

2002-11-04

2004-06-15

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185240

Reexamination Certificate

active

06751125

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a memory and in particular to a read operation of a memory.
2. Description of the Related Art
Some memories such as non-volatile memories implement single transistor memory cells for storing data. An example of a type of transistor that may be used in such memory cells is a transistor having a gate dielectric that includes an oxide
itride/oxide (ONO) stack, such as, e.g., a silicon oxide nitride oxide silicon (SONOS) transistor. With such transistors, charge may be stored in the nitride layer to represent a value stored in the memory cell.
One problem with the use of such transistors in a memory array is that a read of a cell of the array may disturb the amount of charge stored in that cell as well as in other cells of the array. This read disturb may be caused by the voltages applied to the cell terminals during a read operation. For example, the voltage applied to the word line may generate an electric field across the transistor dielectric leading to a change in the charge stored in the dielectric. If the charge entering or leaving the dielectric becomes too great, the threshold voltage (Vt) may be altered such that the cell will not provide the proper value when read.
FIG. 1
is a diagram of an erased state threshold voltage distribution for a prior art, single transistor cell, memory array. In a properly functioning array, the threshold voltages of the transistors of the array having an erased state are within a distribution
105
that is located in a region between 0V and the read voltage (Vr). Distribution
105
is located sufficiently below Vr (by the amount which is indicated by “Gate Drive” in
FIG. 1
) such that each transistor having an erased state provides a sufficient read current to be sensed by a sense amplifier (not shown).
When a read voltage (Vr) is applied to the gate of a transistor, it causes an electric field across the storage dielectric (ONO stack) which can change the amount of charge stored in the nitride, thereby raising the threshold voltage (Vt) of the transistor. The magnitude of the electric field is dependent upon the magnitude of the read voltage (Vr) and the thickness of the dielectric layers in the ONO stack. The magnitude of the electric field is also dependent upon the charge neutral threshold voltage of the transistor which is dependent upon the doping of the channel and the effective gate dielectric thickness, as well as other factors.
Distribution
105
is also located sufficiently above 0 Volts (V) such that all of the transistors having an erased state in a selected column and unselected row will not generate leakage current during a read of a cell in a selected column and a selected row.
Another problem with such transistors is that as the operating voltages of memory arrays decrease, there may be insufficient voltage range between 0V and Vr to have a workable distribution where all transistors have an erased state which will provide sufficient gate drive and immunity to leakage current during a read.


REFERENCES:
patent: 5416738 (1995-05-01), Shrivastava
patent: 5432738 (1995-07-01), Watsuji et al.
patent: 5789776 (1998-08-01), Lancaster et al.
patent: 5841700 (1998-11-01), Chang
patent: 6490196 (2002-12-01), Hsu et al.
patent: 1 168 434 (2002-01-01), None

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