Flip-chip type semiconductor device for reducing signal skew

Details Flip-chip type semiconductor device for reducing signal skew Flip-chip type semiconductor device for reducing signal skew

2002-08-20

2004-02-03

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S203000, C257S775000

Reexamination Certificate

active

06686615

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a flip-chip type semiconductor device for reducing signal skew and, more particularly, to a flip-chip type semiconductor device having equal lengths of redistribution traces for reducing signal skew.
BACKGROUND OF THE INVENTION
With recent remarkable advances in the semiconductor industry, the features of IC devices are continuously reduced and the circuit densities have correspondingly increased. As a result, the operation speed is also increased. As the operation speed of the IC device increases, the requirement for a shorter time traveling between I/O pins becomes higher. Signal misjudged, delayed, or even lost occurs when signals are unable to traverse from one point to another simultaneously according to system clock. Therefore, to pursue ways to effectively resolve the signal skew problem in the high-speed IC device industry is imperative.
In general, high-speed IC device (die) with flip chip type has bumps to combine with a printed wiring board to acquire a shorter transmission path and a higher I/O density. Usually there are a plurality of distribution metal traces connecting with bumps on an active surface of the IC device (die). However, if the metal traces of die are not properly designed, time delays between signal transmissions will occur, resulting in signal skew. To reduce signal skew in bumped die, a solution was proclaimed in the U.S. Pat. No. 6,025,647 entitled “APPARATUS FOR EQUALIZING SIGNAL PARAMETERS IN FLIP CHIP REDISTRIBUTION LAYERS”, as shown is
FIG. 1
, which is an exemplary portion of an equalized redistribution layer. It referred to an equalized redistribution layout cell
306
having bumping pads
304
a
and
304
c
as the outer connected points of signal
1
and signal
4
respectively. The bumping pad
304
a
is connected to a narrower redistribution trace
406
which conducted to a bonding pad
202
b
for a shorter distance, while the bumping pad
304
c
is connected to a wider redistribution trace
404
which conducted to a bonding pad
202
f
for a longer distance. The lengthy trace
404
has wider trace so as to control and ensure that the redistribution traces
404
and
406
have the same characteristic impedance to reduce signal skew. Yet to acquire the corresponding widths of the different lengths of redistribution traces, the characteristic impedance had to be deliberately calculated. This increases the difficulties of circuit designs, and so as to the manufacture.
SUMMARY OF THE INVENTION
A main purpose of the present invention is to supply a flip chip type semiconductor device for reducing signal skew. Redistribution traces with equal lengths are applied to acquire simple circuit design to reduce signal skew.
A second purpose of the present invention is to supply a flip chip type semiconductor device having a redistribution trace with narrow width to pass through the narrow spacing between laser fuse windows. The redistribution trace with narrower width is thicker than other traces to equalize the characteristic impedance, and so as to avoid signal skew and difficulties in calculation.
In accordance with the present invention, a flip chip type semiconductor device for reducing signal skew mainly comprises a chip formed with circuits and a plurality of bonding pads on a surface. A redistribution layer includes a plurality of bumping pads and redistribution traces arranged on the surface of the chip. The redistribution traces are configured to connect the bonding pads to the corresponding bumping pads. Wherein each of the redistribution traces has equal length selected to reduce signal skew. A passivation layer is formed on the surface of the chip to cover the redistribution traces but expose surfaces of the bumping pads for forming bumps.


REFERENCES:
patent: 5994766 (1999-11-01), Shenoy et al.
patent: 6025647 (2000-02-01), Shenoy et al.

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