Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-11-13
2004-11-09
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S089000
Reexamination Certificate
active
06816144
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data line drive circuit for a panel display, and more specifically to a panel display data line drive circuit capable of driving, with a low power consumption, a panel display typified by a liquid crystal display such as a TFT-LCD (thin film transistor driven liquid crystal display) and an active matrix drive type organic EL display.
At present, liquid crystal displays are widely used in various fields. When the liquid crystal display is incorporated into a portable instrument, it is demanded to make a power consumption of the portable instrument as small as possible, in order to allow to unintermittently utilize the portable instrument with no necessity of an electric charging. As one means for achieving this demand, a power consumption of the liquid crystal display is required to be reduced to a minimum. For this purpose, various power saving approaches have been proposed, and some of them has been reduced into practice.
A liquid crystal display incorporated in a hand-held type portable instrument such as a PDA, a portable game instrument and a portable telephone has a relatively small display screen size and correspondingly a small number of pixels. In the case of driving a small-size TFT-LCD panel having a relatively small number of pixels, a horizontal scan frequency is low and a load capacitance of the TFT-LCD panel is also small. Therefore, in a power consumption of a data line driving circuit for the liquid crystal display, a static consumed electric power of an output buffer takes a large proportion.
In brief, the power consumption of the data line driving circuit for the TFT-LCD panel is divided into an electric power for charging a data line in the TFT-LCD panel, and an electric power consumed by the data line driving circuit itself. In the case of the small-size TFT-LCD panel having a relatively small number of pixels, since a load capacitance of the data line is small, the electric power for charging the data line is correspondingly small. As a result, the proportion of the electric power consumed by the data line driving circuit itself to a whole power consumption of the data line driving circuit for the TFT-LCD panel, is large. In addition, the proportion of the static consumed electric power of the output buffer to the electric power consumed by the data line driving circuit itself is large. A similar problem occurs in a data line driving circuit configured to drive a data line in accordance with a gray-scale voltage in a small display panel such as an active matrix drive type organic EL display, other than the liquid crystal display.
Here, examining a prior art data line driving circuit for a liquid crystal display, JP-A-07-013528 and JP-A-07-104703 propose to drive the LCD panel in a time division manner. However, this structure is intended to reduce the number of external interconnections between the LCD panel and a column driver circuit discrete therefrom.
Furthermore, the data line driving circuits of these patent publications are constructed to simultaneously and once precharge all data lines to a fixed voltage corresponding to for example a high level, before each data line is driven to a designated drive voltage, and thereafter to discharge each precharged data line to the designated drive voltage. This is based on a recognition that a discharging time of the data line is shorter than a charging time of the data line. This procedure can make it possible to shorten a time required for driving the data line to the designated drive voltage. However, since all the data lines are simultaneously precharged to the fixed voltage corresponding to for example the high level regardless of the designated drive voltage, when the designated drive voltage is near to a low level, there is possibility that the time required for driving to the designated drive voltage is rather longer than the case of driving to the designated drive voltage with no precharging.
Alternatively, JP-A-07-173506 proposes to supply an output of a digital-to-analog converter to the data line in a time division manner. However, this structure is intended to prevent the scale-up of the whole data line drive circuit occurring with increase in the number of pixels, and to reduce the power consumption.
Furthermore, JP-A-07-173506 proposes, as a second invention, to precharge the data lines to a maximum drive voltage when the drive output voltage is not smaller than an intermediate drive voltage, and to a minimum drive voltage when the drive output voltage is not larger than an intermediate drive voltage. However, it does not disclose a specific method for selecting the precharge voltage.
In addition, JP-A-11-119741 proposes to precharge one of adjacent data lines to a maximum drive voltage, and then, to drive the precharged data line to a designated drive voltage by use of an operational amplifier having a high current drawing capacity, and further, to precharge the other of the adjacent data lines to a minimum drive voltage, and then, to drive the precharged data line to a designated drive voltage by use of an operational amplifier having a high current supplying capacity, so that a voltage variation between opposing electrodes can be suppressed, and a display unevenness is reduced. According to this disclosed invention, each data line is ceaselessly precharged to either one fixed voltage of the maximum drive voltage and the minimum drive voltage, regardless of a designated drive voltage to be applied to the data line concerned.
None of the above mentioned prior art examples is intended to reduce the static consumed electric power in the output buffer in the data line drive circuit for the liquid crystal display. Accordingly, heretofore, there is no data line drive circuit for the liquid crystal display, which reduces the power consumption of the liquid crystal display, by reducing the static consumed electric power in the output buffer in the data line drive circuit for the liquid crystal display.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a data line drive circuit for a panel display, capable of driving the panel display with a reduced power consumption, by reducing the static consumed electric power in the output buffer in the data line drive circuit for the panel display such as a liquid crystal display.
According to a first aspect of the present invention, there is provided a data line drive circuit for a panel display, comprising a selection means receiving a plurality of voltages corresponding to each plurality of data lines, of a number of data lines of the panel display, analog buffers each provided in common for a plurality of data lines, for receiving and outputting the voltage alternatively selected by the selection means, a distribution means receiving an output of each analog buffer for selectively distributing the output of the analog buffer to a selected one of the plurality of data lines, a precharge means provided for each of the plurality of data lines, for precharging a corresponding data line to either a high drive voltage or a low drive voltage, in accordance with at least the most significant bit signal of a digital data corresponding to the corresponding data line, and a control means for controlling the selection means, the distribution means and the precharge means, wherein each scan line selection period includes a precharge period and a plurality of writing periods succeeding to the precharge period, and during the precharge period, the control means controls the distribution means to separate the output of the analog buffers from all the data lines, and activates each precharge means to precharge all the data lines, and during the plurality of writing periods, the control means inactivates each precharge means and controls the selection means and the distribution means in such a manner that during a first writing period of the plurality of writing periods, the voltage corresponding to a first data line of the plurality of data lines is supplied to the ana
NEC Corporation
Nguyen Chanh
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