Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2001-10-10
2004-08-10
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S773000, C257S774000
Reexamination Certificate
active
06774486
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to structures for interconnecting integrated circuits disposed on opposite sides of an insulating substrate. More specifically, the present invention relates to methods and apparatus for enabling electronic components mounted on both sides of an insulating substrate to communicate electrically without having to remove areas of the substrate to form a via.
BACKGROUND OF THE INVENTION
A main focus of the contemporary semiconductor industry is miniaturization, which is furthered by increasing the density at which integrated circuits are mounted on a substrate, such as a printed circuit board. Miniaturization enables the design and manufacture of increasingly smaller and more compact devices such as hand-held computers, personal data assistants (PDA) and portable telecommunications devices.
One way to satisfy the demand for increased integrated circuit density is to attach integrated circuits to opposing sides of a dielectric circuit board. A technique developed by the semiconductor industry to couple integrated circuits positioned on opposite sides of a circuit board to each other has been the creation of conductive vias through circuit boards.
FIG. 1
is a partial isometric view of a circuit board
1
comprising a substrate
8
with holes
10
extending through its thickness
11
in any desired arrangement according to the prior art. The substrate
8
may comprise a BT or FR dielectric core, and the methods used to make the holes
10
include drilling, etching and laser ablation.
The circuit board
1
is shown in greater detail in
FIG. 2
, which is a partial cross-sectional view of the circuit board
1
at a later stage of production. After the holes
10
have been formed in the substrate
8
, they are plated to form conductive linings
12
. The conductive linings
12
extend from the first surface
15
of the substrate
8
to the second surface
16
of the substrate
8
. The lining
12
is generally comprised of copper, but any other conductive material may be used. Conductive traces
13
are also deposited on the first and second surfaces
15
and
16
of the substrate
8
. The conductive traces
13
couple integrated circuits to other integrated circuits mounted on the same surface
15
,
16
. Additionally, the conductive traces
13
couple integrated circuits to the linings
12
.
A solder mask
14
may then be applied to both the first surface
15
and the second surface
16
to insulate conductive traces
13
and conductive via linings
12
, and to protect them from deleterious environmental factors such as dust or moisture. Areas of the traces
13
and linings
12
to which conductive integrated circuit leads will be soldered are left uncoated by the solder mask
14
. Integrated circuits (not shown) are then soldered to the traces
13
on the first surface
15
and the second surface
16
.
There are several problems associated with this type of prior art technique however, with perhaps the most significant being the limited density at which vias may be formed. Each via must inherently have a diameter
18
greater than the diameter
17
of its hole
10
to enable traces
13
to connect to the via. This outer diameter
18
of the contact surface, or contact pad
19
, typically amounts to twice the diameter
17
of the hole
10
. Therefore, even if the diameter of the holes
10
could be decreased, the density of the vias would still be limited by the outer diameter
18
of the contact pad
19
.
Presently, holes
10
can be drilled with diameters as small as 50 &mgr;m. This limitation arises due to difficulties in forming narrow holes
10
in the substrate
8
, as well as difficulties in plating the inner surfaces of the holes
10
. As a consequence, after the addition of the necessary capture pad, the prior art cannot create vias with diameters of less than 100 &mgr;m. This significantly constrains efforts to increase circuit board density, and prevents the development of smaller and more compact electronic devices.
What is needed is a method of electrically coupling two integrated circuits on opposite sides of a circuit board without the prior art solution of creating and filling holes in the circuit board.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board. The conduction elements extend from one surface of the circuit board to the other. Conductive traces coupled to integrated circuits make contact with the conduction elements to allow integrated circuits mounted on opposite surfaces of the board to be coupled to each other.
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Dorsey & Whitney LLP
Micro)n Technology, Inc.
Soward Ida M
Zarabian Amir
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